[U-Boot] Please investigate T2080QDS U-Boot

[york sun]

I went back to last several releases and saw the same. Do we have it in SDK U-Boot?

York


-------- Original Message --------
From: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
Sent: Thursday, July 14, 2016 06:40 PM
To: york sun <york.sun at nxp.com>,Shengzhou Liu <shengzhou.liu at nxp.com>
Subject: RE: Please investigate T2080QDS U-Boot
CC: u-boot at lists.denx.de


Hi York,

I am just curious about this issue.

Was it coming earlier on this board or started coming now.
I guess you can still access NAND flash on the board.


Regards,
Prabhakar

> -----Original Message-----
> From: york sun
> Sent: Thursday, July 14, 2016 10:33 PM
> To: Shengzhou Liu <shengzhou.liu at nxp.com>
> Cc: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>; u-
> boot at lists.denx.de
> Subject: Please investigate T2080QDS U-Boot
>
> Shengzhou,
>
> Can you investigate this message on T2080QDS (see log below)? Looks like
> some issue with NAND flash. It doesn't happen on T4240QDS.
>
> York
>
> U-Boot 2016.07-00067-gb8e5997 (Jul 14 2016 - 09:58:11 -0700)
>
> CPU0:  T2080E, Version: 1.1, (0x85380011)
> Core:  e6500, Version: 2.0, (0x80400120)
> Clock Configuration:
>         CPU0:1800 MHz, CPU1:1800 MHz, CPU2:1800 MHz, CPU3:1800 MHz,
>         CCB:600  MHz,
>         DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous),
> IFC:150  MHz
>         FMAN1: 700 MHz
>         QMAN:  300 MHz
>         PME:   600 MHz
> L1:    D-cache 32 KiB enabled
>         I-cache 32 KiB enabled
> Reset Configuration Word (RCW):
>         00000000: 0c070012 0e000000 00000000 00000000
>         00000010: 6c2d0002 00000000 ec027000 c1000000
>         00000020: 00000000 00000000 00000000 000307fc
>         00000030: 00000000 00000000 00000000 00000004
> Board: T2080QDS, Sys ID: 0x28, Board Arch: V1, Board Version: A, boot
> from vBank4
> FPGA: v11 (T1040QDS_2014_0318_1724), build 317 on Tue Mar 18 21:24:26
> 2014
> SERDES Reference Clocks:
> SD1_CLK1=156.25MHZ, SD1_CLK2=100.00MHz
> SD2_CLK1=100.00MHz, SD2_CLK2=100.00MHz
> I2C:   ready
> SPI:   ready
> DRAM:  Initializing....using SPD
> Detected UDIMM
> 6 GiB left unmapped
> 8 GiB (DDR3, 64-bit, CL=13, ECC on)
>         DDR Chip-Select Interleaving Mode: CS0+CS1
> Flash: 128 MiB
> L2:    2 MiB enabled
> Corenet Platform Cache: 512 KiB enabled
> Using SERDES1 Protocol: 108 (0x6c)
> Using SERDES2 Protocol: 45 (0x2d)
> SRIO1: enabled
> SRIO2: enabled
> SEC0: RNG instantiated
> NAND:  fsl_ifc_read_byte beyond end of buffer
> fsl_ifc_read_byte beyond end of buffer
> fsl_ifc_read_byte beyond end of buffer
> fsl_ifc_read_byte beyond end of buffer
> fsl_ifc_read_byte beyond end of buffer
> fsl_ifc_read_byte beyond end of buffer
> fsl_ifc_read_byte beyond end of buffer
> fsl_ifc_read_byte beyond end of buffer
> fsl_ifc_read_byte beyond end of buffer
> fsl_ifc_read_byte beyond end of buffer
> fsl_ifc_read_byte beyond end of buffer
> fsl_ifc_read_byte beyond end of buffer
> fsl_ifc_read_byte beyond end of buffer
> fsl_ifc_read_byte beyond end of buffer
> fsl_ifc_read_byte beyond end of buffer
> fsl_ifc_read_byte beyond end of buffer
> fsl_ifc_read_byte beyond end of buffer
> fsl_ifc_read_byte beyond end of buffer
> fsl_ifc_read_byte beyond end of buffer
> fsl_ifc_read_byte beyond end of buffer