[U-Boot] [PATCH v2 1/5] mpc85xx/powerpc:cpu_init: Modified the errata A006261 according to endianness

[Marek Vasut]

On 07/18/2016 05:47 AM, Sriram Dash wrote:

Can you please be consistent about the tag spacing in the subject ?
Each : must be followed by space.

> Modifies errata implementation due to the fact that P3041,
> P5020, and P5040 are all big endian for the USB PHY registers, but
> they were specified little endian.
>
> Signed-off-by: Sriram Dash <sriram.dash at nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bhagat at nxp.com>
> ---
> Changes in v2:
>   - Adds the errata number to title of patch
>   - Makes separate patch for addition of errata to specific Socs.
>
>
>  arch/powerpc/cpu/mpc85xx/cpu_init.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
> index 61f5639..61dedfc 100644
> --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
> +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
> @@ -114,10 +114,10 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
>  	setbits_be32(&usb_phy->config2,
>  		     CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
>
> -	temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
> +	temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
>  	out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
>
> -	temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
> +	temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
>  	out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
>  #endif
>  }
>


-- 
Best regards,
Marek Vasut