[U-Boot] [PATCH 0/4] dra7xx: QSPI: Increase SPI bus speed.

[Vignesh R]

By configuring DPLL_PER_HS13 divider value to provide 76.8MHz clock as
QSPI fclk on dra7xx, it is possible to operate SPI slave clock at
768.MHz which is the maximum supported frequency as per AM572x DM
SPRS953A. This helps to increase flash read speed by ~2MB/s.

Tested  on DRA74 Rev G & H, DRA72 Rev B & C EVMs.


Lokesh Vutla (1):
  ARM: dra7xx: Change DPLL_PER_HS13 divider value

Vignesh R (3):
  spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock
  configs: dra7xx: Update QSPI speed to 76.8MHz
  ARM: dts: dra7xx: Update spi-max-frequency for QSPI

 arch/arm/cpu/armv7/omap5/hw_data.c |  2 +-
 arch/arm/dts/dra7-evm.dts          |  2 +-
 arch/arm/dts/dra72-evm.dts         |  2 +-
 drivers/spi/ti_qspi.c              | 17 ++++++++++++-----
 include/configs/dra7xx_evm.h       |  2 +-
 5 files changed, 16 insertions(+), 9 deletions(-)

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2.9.2