[U-Boot] [PATCH 7/7] boston: Introduce support for the MIPS Boston development board

Daniel Schwierzeck daniel.schwierzeck at gmail.com
Wed Jul 27 13:37:12 CEST 2016



Am 27.07.2016 um 00:24 schrieb Paul Burton:
> This patch introduces support for building U-Boot to run on the MIPS
> Boston development board. This is a board built around an FPGA & an
> Intel EG20T Platform Controller Hub, used largely as part of the
> development of new CPUs and their software support. It is essentially
> the successor to the older MIPS Malta board.
> 
> Signed-off-by: Paul Burton <paul.burton at imgtec.com>
> 
> ---
> 
>  arch/mips/Kconfig                   |  16 +++
>  arch/mips/dts/Makefile              |   1 +
>  arch/mips/dts/img,boston.dts        | 225 ++++++++++++++++++++++++++++++++++++
>  board/imgtec/boston/Kconfig         |  16 +++
>  board/imgtec/boston/MAINTAINERS     |   6 +
>  board/imgtec/boston/Makefile        |  10 ++
>  board/imgtec/boston/boston-lcd.h    |  21 ++++
>  board/imgtec/boston/boston-regs.h   |  47 ++++++++
>  board/imgtec/boston/checkboard.c    |  29 +++++
>  board/imgtec/boston/ddr.c           |  30 +++++
>  board/imgtec/boston/early_init.c    |  61 ++++++++++
>  board/imgtec/boston/lowlevel_init.S |  56 +++++++++
>  configs/boston_defconfig            |  41 +++++++
>  include/configs/boston.h            |  69 +++++++++++
>  14 files changed, 628 insertions(+)
>  create mode 100644 arch/mips/dts/img,boston.dts
>  create mode 100644 board/imgtec/boston/Kconfig
>  create mode 100644 board/imgtec/boston/MAINTAINERS
>  create mode 100644 board/imgtec/boston/Makefile
>  create mode 100644 board/imgtec/boston/boston-lcd.h
>  create mode 100644 board/imgtec/boston/boston-regs.h
>  create mode 100644 board/imgtec/boston/checkboard.c
>  create mode 100644 board/imgtec/boston/ddr.c
>  create mode 100644 board/imgtec/boston/early_init.c
>  create mode 100644 board/imgtec/boston/lowlevel_init.S
>  create mode 100644 configs/boston_defconfig
>  create mode 100644 include/configs/boston.h
> 
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 21066f0..7ba0ef2 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -73,9 +73,25 @@ config MACH_PIC32
>  	select OF_CONTROL
>  	select DM
>  
> +config TARGET_BOSTON
> +	bool "Support Boston"
> +	select DM
> +	select DM_SERIAL
> +	select OF_CONTROL
> +	select MIPS_L1_CACHE_SHIFT_6
> +	select SUPPORTS_BIG_ENDIAN
> +	select SUPPORTS_LITTLE_ENDIAN
> +	select SUPPORTS_CPU_MIPS32_R1
> +	select SUPPORTS_CPU_MIPS32_R2
> +	select SUPPORTS_CPU_MIPS32_R6
> +	select SUPPORTS_CPU_MIPS64_R1
> +	select SUPPORTS_CPU_MIPS64_R2
> +	select SUPPORTS_CPU_MIPS64_R6
> +
>  endchoice
>  
>  source "board/dbau1x00/Kconfig"
> +source "board/imgtec/boston/Kconfig"
>  source "board/imgtec/malta/Kconfig"
>  source "board/micronas/vct/Kconfig"
>  source "board/pb1x00/Kconfig"
> diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
> index 2f04d73..6a5e43e 100644
> --- a/arch/mips/dts/Makefile
> +++ b/arch/mips/dts/Makefile
> @@ -4,6 +4,7 @@
>  
>  dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
>  dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
> +dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
>  dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
>  dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
>  dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
> diff --git a/arch/mips/dts/img,boston.dts b/arch/mips/dts/img,boston.dts
> new file mode 100644
> index 0000000..e4e0f28
> --- /dev/null
> +++ b/arch/mips/dts/img,boston.dts
> @@ -0,0 +1,225 @@
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/mips-gic.h>
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	compatible = "img,boston";
> +
> +	chosen {
> +		stdout-path = &uart0;
> +	};
> +
> +	aliases {
> +		clk_sys = &clk_sys;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu at 0 {
> +			device_type = "cpu";
> +			compatible = "img,mips";
> +			reg = <0>;
> +			clocks = <&clk_sys>;
> +		};
> +	};
> +
> +	memory at 0 {
> +		device_type = "memory";
> +		reg = <0x00000000 0x10000000>;
> +	};
> +
> +	clk_sys: clock {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <10000000>;
> +		u-boot,dm-pre-reloc;
> +	};
> +
> +	axi4 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <>;
> +
> +		gic: interrupt-controller {
> +			compatible = "mti,gic";
> +
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +
> +			timer {
> +				compatible = "mti,gic-timer";
> +				interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
> +				clocks = <&clk_sys>;
> +			};
> +		};
> +
> +		plat_regs: system-controller at 17ffd000 {
> +			compatible = "img,boston-platform-regs", "syscon";
> +			reg = <0x17ffd000 0x1000>;
> +		};
> +
> +		reboot: syscon-reboot {
> +			compatible = "syscon-reboot";
> +			regmap = <&plat_regs>;
> +			offset = <0x10>;
> +			mask = <0x10>;
> +		};
> +
> +		uart0: uart at 17ffe000 {
> +			compatible = "ns16550a";
> +			reg = <0x17ffe000 0x1000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			clocks = <&clk_sys>;
> +
> +			u-boot,dm-pre-reloc;
> +		};
> +
> +		lcd: lcd at 17fff000 {
> +			compatible = "img,boston-lcd";
> +			reg = <0x17fff000 0x8>;
> +		};
> +
> +		pci0: pci at 10000000 {
> +			status = "disabled";
> +			compatible = "xlnx,axi-pcie-host-1.00.a";
> +			device_type = "pci";
> +			reg = <0x10000000 0x2000000>;
> +
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			#interrupt-cells = <1>;
> +
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			ranges = <0x02000000 0 0x40000000
> +				  0x40000000 0 0x40000000>;
> +
> +			interrupt-map-mask = <0 0 0 7>;
> +			interrupt-map = <0 0 0 1 &pci0_intc 0>,
> +					<0 0 0 2 &pci0_intc 1>,
> +					<0 0 0 3 &pci0_intc 2>,
> +					<0 0 0 4 &pci0_intc 3>;
> +
> +			pci0_intc: interrupt-controller {
> +				interrupt-controller;
> +				#address-cells = <0>;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		pci1: pci at 12000000 {
> +			status = "disabled";
> +			compatible = "xlnx,axi-pcie-host-1.00.a";
> +			device_type = "pci";
> +			reg = <0x12000000 0x2000000>;
> +
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			#interrupt-cells = <1>;
> +
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			ranges = <0x02000000 0 0x20000000
> +				  0x20000000 0 0x20000000>;
> +
> +			interrupt-map-mask = <0 0 0 7>;
> +			interrupt-map = <0 0 0 1 &pci1_intc 0>,
> +					<0 0 0 2 &pci1_intc 1>,
> +					<0 0 0 3 &pci1_intc 2>,
> +					<0 0 0 4 &pci1_intc 3>;
> +
> +			pci1_intc: interrupt-controller {
> +				interrupt-controller;
> +				#address-cells = <0>;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		pci2: pci at 14000000 {
> +			compatible = "xlnx,axi-pcie-host-1.00.a";
> +			device_type = "pci";
> +			reg = <0x14000000 0x2000000>;
> +
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			#interrupt-cells = <1>;
> +
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			ranges = <0x02000000 0 0x16000000
> +				  0x16000000 0 0x100000>;
> +
> +			interrupt-map-mask = <0 0 0 7>;
> +			interrupt-map = <0 0 0 1 &pci2_intc 0>,
> +					<0 0 0 2 &pci2_intc 1>,
> +					<0 0 0 3 &pci2_intc 2>,
> +					<0 0 0 4 &pci2_intc 3>;
> +
> +			pci2_intc: interrupt-controller {
> +				interrupt-controller;
> +				#address-cells = <0>;
> +				#interrupt-cells = <1>;
> +			};
> +
> +			pci2_root at 0,0,0 {
> +				compatible = "pci10ee,7021";
> +				reg = <0x00000000 0 0 0 0>;
> +
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				#interrupt-cells = <1>;
> +
> +				eg20t_bridge at 1,0,0 {
> +					compatible = "pci8086,8800";
> +					reg = <0x00010000 0 0 0 0>;
> +
> +					#address-cells = <3>;
> +					#size-cells = <2>;
> +					#interrupt-cells = <1>;
> +
> +					eg20t_mac at 2,0,1 {
> +						compatible = "pci8086,8802";
> +						reg = <0x00020100 0 0 0 0>;
> +						phy-reset-gpios = <&eg20t_gpio 6 GPIO_ACTIVE_LOW>;
> +					};
> +
> +					eg20t_gpio: eg20t_gpio at 2,0,2 {
> +						compatible = "pci8086,8803";
> +						reg = <0x00020200 0 0 0 0>;
> +
> +						gpio-controller;
> +						#gpio-cells = <2>;
> +					};
> +
> +					eg20t_i2c at 2,12,2 {
> +						compatible = "pci8086,8817";
> +						reg = <0x00026200 0 0 0 0>;
> +
> +						#address-cells = <1>;
> +						#size-cells = <0>;
> +
> +						rtc at 0x68 {
> +							compatible = "st,m41t81s";
> +							reg = <0x68>;
> +						};
> +					};
> +				};
> +			};
> +		};
> +	};
> +};
> diff --git a/board/imgtec/boston/Kconfig b/board/imgtec/boston/Kconfig
> new file mode 100644
> index 0000000..ab76a3c
> --- /dev/null
> +++ b/board/imgtec/boston/Kconfig
> @@ -0,0 +1,16 @@
> +if TARGET_BOSTON
> +
> +config SYS_BOARD
> +	default "boston"
> +
> +config SYS_VENDOR
> +	default "imgtec"
> +
> +config SYS_CONFIG_NAME
> +	default "boston"
> +
> +config SYS_TEXT_BASE
> +	default 0x9fc00000 if 32BIT
> +	default 0xffffffff9fc00000 if 64BIT
> +
> +endif
> diff --git a/board/imgtec/boston/MAINTAINERS b/board/imgtec/boston/MAINTAINERS
> new file mode 100644
> index 0000000..30dd481
> --- /dev/null
> +++ b/board/imgtec/boston/MAINTAINERS
> @@ -0,0 +1,6 @@
> +BOSTON BOARD
> +M:	Paul Burton <paul.burton at imgtec.com>
> +S:	Maintained
> +F:	board/imgtec/boston/
> +F:	include/configs/boston.h
> +F:	configs/boston_defconfig
> diff --git a/board/imgtec/boston/Makefile b/board/imgtec/boston/Makefile
> new file mode 100644
> index 0000000..b7125b5
> --- /dev/null
> +++ b/board/imgtec/boston/Makefile
> @@ -0,0 +1,10 @@
> +#
> +# Copyright (C) 2016 Imagination Technologies
> +#
> +# SPDX-License-Identifier:	GPL-2.0
> +#
> +
> +obj-y += checkboard.o
> +obj-y += ddr.o
> +obj-y += early_init.o
> +obj-y += lowlevel_init.o
> diff --git a/board/imgtec/boston/boston-lcd.h b/board/imgtec/boston/boston-lcd.h
> new file mode 100644
> index 0000000..9f5c1b9
> --- /dev/null
> +++ b/board/imgtec/boston/boston-lcd.h
> @@ -0,0 +1,21 @@
> +/*
> + * Copyright (C) 2016 Imagination Technologies
> + *
> + * SPDX-License-Identifier:	GPL-2.0
> + */
> +
> +#ifndef __BOARD_BOSTON_LCD_H__
> +#define __BOARD_BOSTON_LCD_H__
> +
> +/**
> + * lowlevel_display() - Display a message on Boston's LCD
> + * @msg: The string to display
> + *
> + * Display the string @msg on the 7 character LCD display of the Boston board.
> + * This is typically used for debug or to present some form of status
> + * indication to the user, allowing faults to be identified when things go
> + * wrong early enough that the UART isn't up.
> + */
> +void lowlevel_display(const char msg[static 8]);
> +
> +#endif /* __BOARD_BOSTON_LCD_H__ */
> diff --git a/board/imgtec/boston/boston-regs.h b/board/imgtec/boston/boston-regs.h
> new file mode 100644
> index 0000000..c33535e
> --- /dev/null
> +++ b/board/imgtec/boston/boston-regs.h
> @@ -0,0 +1,47 @@
> +/*
> + * Copyright (C) 2016 Imagination Technologies
> + *
> + * SPDX-License-Identifier:	GPL-2.0
> + */
> +
> +#ifndef __BOARD_BOSTON_REGS_H__
> +#define __BOARD_BOSTON_REGS_H__
> +
> +#define BOSTON_PLAT_BASE		0x17ffd000
> +#define BOSTON_LCD_BASE			0x17fff000
> +
> +/*
> + * Platform Register Definitions
> + */
> +#define BOSTON_PLAT_CORE_CL		0x04
> +
> +#define BOSTON_PLAT_DDR3STAT		0x14
> +# define BOSTON_PLAT_DDR3STAT_CALIB	(1 << 2)
> +
> +#define BOSTON_PLAT_MMCMDIV		0x30
> +# define BOSTON_PLAT_MMCMDIV_CLK0DIV	(0xff << 0)
> +# define BOSTON_PLAT_MMCMDIV_INPUT	(0xff << 8)
> +# define BOSTON_PLAT_MMCMDIV_MUL	(0xff << 16)
> +# define BOSTON_PLAT_MMCMDIV_CLK1DIV	(0xff << 24)
> +
> +#define BOSTON_PLAT_DDRCONF0		0x38
> +# define BOSTON_PLAT_DDRCONF0_SIZE	(0xf << 0)
> +
> +#ifndef __ASSEMBLY__
> +
> +#include <asm/io.h>
> +
> +#define BUILD_PLAT_ACCESSORS(offset, name)				\
> +static inline uint32_t read_boston_##name(void)				\
> +{									\
> +	uint32_t *reg = (void *)CKSEG1ADDR(BOSTON_PLAT_BASE) + (offset);\
> +	return __raw_readl(reg);					\
> +}
> +
> +BUILD_PLAT_ACCESSORS(BOSTON_PLAT_CORE_CL, core_cl)
> +BUILD_PLAT_ACCESSORS(BOSTON_PLAT_MMCMDIV, mmcmdiv)
> +BUILD_PLAT_ACCESSORS(BOSTON_PLAT_DDRCONF0, ddrconf0)
> +
> +#endif /* !__ASSEMBLY__ */
> +
> +#endif /* __BOARD_BOSTON_REGS_H__ */
> diff --git a/board/imgtec/boston/checkboard.c b/board/imgtec/boston/checkboard.c
> new file mode 100644
> index 0000000..417ac4e
> --- /dev/null
> +++ b/board/imgtec/boston/checkboard.c
> @@ -0,0 +1,29 @@
> +/*
> + * Copyright (C) 2016 Imagination Technologies
> + *
> + * SPDX-License-Identifier:	GPL-2.0
> + */
> +
> +#include <common.h>
> +
> +#include <asm/mipsregs.h>
> +
> +#include "boston-lcd.h"
> +#include "boston-regs.h"
> +
> +int checkboard(void)
> +{
> +	u32 changelist;
> +
> +	lowlevel_display("U-boot  ");
> +
> +	printf("Board: MIPS Boston\n");
> +
> +	printf("CPU:   0x%08x", read_c0_prid());
> +	changelist = read_boston_core_cl();
> +	if (changelist > 1)
> +		printf(" cl%x", changelist);
> +	putc('\n');
> +
> +	return 0;
> +}
> diff --git a/board/imgtec/boston/ddr.c b/board/imgtec/boston/ddr.c
> new file mode 100644
> index 0000000..7caed4b
> --- /dev/null
> +++ b/board/imgtec/boston/ddr.c
> @@ -0,0 +1,30 @@
> +/*
> + * Copyright (C) 2016 Imagination Technologies
> + *
> + * SPDX-License-Identifier:	GPL-2.0
> + */
> +
> +#include <common.h>
> +
> +#include <asm/addrspace.h>
> +
> +#include "boston-regs.h"
> +
> +phys_size_t initdram(int board_type)
> +{
> +	u32 ddrconf0 = read_boston_ddrconf0();
> +
> +	return (phys_size_t)(ddrconf0 & BOSTON_PLAT_DDRCONF0_SIZE) << 30;
> +}
> +
> +ulong board_get_usable_ram_top(ulong total_size)
> +{
> +	DECLARE_GLOBAL_DATA_PTR;
> +
> +	if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) {
> +		/* 2GB wrapped around to 0 */
> +		return CKSEG0ADDR(256 << 20);
> +	}
> +
> +	return min_t(unsigned long, gd->ram_top, CKSEG0ADDR(256 << 20));
> +}
> diff --git a/board/imgtec/boston/early_init.c b/board/imgtec/boston/early_init.c
> new file mode 100644
> index 0000000..eac56d6
> --- /dev/null
> +++ b/board/imgtec/boston/early_init.c
> @@ -0,0 +1,61 @@
> +/*
> + * Copyright (C) 2016 Imagination Technologies
> + *
> + * SPDX-License-Identifier:	GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <libfdt.h>
> +
> +#include "boston-regs.h"
> +
> +/**
> + * fixup_dt_clock() - Fixup the system clock frequency in the DT
> + * @fdt: Pointer to the Flattened Device Tree
> + *
> + * Calculate the system clock frequency from the Boston platform registers and
> + * update the clocks representation in the FDT to report the correct frequency.
> + */
> +static void fixup_dt_clock(void *fdt)
> +{
> +	uint32_t mmcmdiv = read_boston_mmcmdiv();
> +	uint32_t in_rate, mul, clk0_div, clk0_rate;
> +	const char *clk_path;
> +	int clk_off, err;
> +
> +	clk_path = fdt_get_alias(fdt, "clk_sys");
> +	if (!clk_path) {
> +		printf("%s: failed to find clk_sys path\n", __func__);
> +		return;
> +	}
> +
> +	clk_off = fdt_path_offset(fdt, clk_path);
> +	if (clk_off < 0) {
> +		printf("%s: failed to find clk_sys offset\n", __func__);
> +		return;
> +	}
> +
> +#define EXT(field) ((mmcmdiv & field) >> (ffs(field) - 1))
> +
> +	in_rate = EXT(BOSTON_PLAT_MMCMDIV_INPUT);
> +	mul = EXT(BOSTON_PLAT_MMCMDIV_MUL);
> +	clk0_div = EXT(BOSTON_PLAT_MMCMDIV_CLK0DIV);
> +
> +#undef EXT
> +
> +	clk0_rate = (in_rate * mul * 1000000) / clk0_div;
> +
> +	err = fdt_setprop_inplace_u32(fdt, clk_off, "clock-frequency",
> +				      clk0_rate);
> +	if (err)
> +		printf("%s: failed to set clock-frequency\n", __func__);
> +}

Couldn't you create a simple clk driver with this code and use that as
clock source? Using the fixed-clk driver and patching the DT properties
seems a little bit strange.

> +
> +int board_early_init_f(void)
> +{
> +	DECLARE_GLOBAL_DATA_PTR;
> +
> +	fixup_dt_clock((void *)gd->fdt_blob);
> +
> +	return 0;
> +}
> diff --git a/board/imgtec/boston/lowlevel_init.S b/board/imgtec/boston/lowlevel_init.S
> new file mode 100644
> index 0000000..b77e9b2
> --- /dev/null
> +++ b/board/imgtec/boston/lowlevel_init.S
> @@ -0,0 +1,56 @@
> +/*
> + * Copyright (C) 2016 Imagination Technologies
> + *
> + * SPDX-License-Identifier:	GPL-2.0
> + */
> +
> +#include <config.h>
> +
> +#include <asm/addrspace.h>
> +#include <asm/asm.h>
> +#include <asm/mipsregs.h>
> +#include <asm/regdef.h>
> +
> +#include "boston-regs.h"
> +
> +.data
> +
> +msg_ddr_cal:	.ascii "DDR Cal "
> +msg_ddr_ok:	.ascii "DDR OK  "
> +
> +.text
> +
> +LEAF(lowlevel_init)
> +	move	s0, ra
> +
> +	PTR_LA	a0, msg_ddr_cal
> +	bal	lowlevel_display
> +
> +	PTR_LI	t0, CKSEG1ADDR(BOSTON_PLAT_BASE)
> +1:	lw	t1, BOSTON_PLAT_DDR3STAT(t0)
> +	andi	t1, t1, BOSTON_PLAT_DDR3STAT_CALIB
> +	beqz	t1, 1b
> +
> +	PTR_LA	a0, msg_ddr_ok
> +	bal	lowlevel_display
> +
> +	move	v0, zero
> +	jr	s0
> +	END(lowlevel_init)
> +
> +LEAF(lowlevel_display)
> +	.set	push
> +	.set	noat
> +	PTR_LI	$1, CKSEG1ADDR(BOSTON_LCD_BASE)

isn't it better to use the symbolic name AT from asm/regdef.h instead of
$1?

> +#ifdef CONFIG_64BIT
> +	ld	k1, 0(a0)
> +	sd	k1, 0($1)
> +#else
> +	lw	k1, 0(a0)
> +	sw	k1, 0($1)
> +	lw	k1, 4(a0)
> +	sw	k1, 4($1)
> +#endif
> +	.set	pop
> +1:	jr	ra
> +	END(lowlevel_display)
> diff --git a/configs/boston_defconfig b/configs/boston_defconfig
> new file mode 100644
> index 0000000..381203a
> --- /dev/null
> +++ b/configs/boston_defconfig
> @@ -0,0 +1,41 @@
> +CONFIG_MIPS=y
> +CONFIG_TARGET_BOSTON=y
> +CONFIG_SYS_LITTLE_ENDIAN=y
> +CONFIG_CPU_MIPS64_R6=y
> +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
> +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
> +CONFIG_MIPS_BOOT_FDT=y
> +CONFIG_DEFAULT_DEVICE_TREE="img,boston"
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_FIT_BEST_MATCH=y
> +CONFIG_OF_STDOUT_VIA_ALIAS=y
> +CONFIG_SYS_NO_FLASH=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_SYS_PROMPT="boston # "
> +# CONFIG_CMD_ELF is not set
> +# CONFIG_CMD_IMLS is not set
> +CONFIG_CMD_GREPENV=y
> +CONFIG_CMD_MEMTEST=y
> +# CONFIG_CMD_LOADB is not set
> +# CONFIG_CMD_LOADS is not set
> +# CONFIG_CMD_FPGA is not set
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_SNTP=y
> +CONFIG_CMD_DNS=y
> +CONFIG_CMD_LINK_LOCAL=y
> +CONFIG_CMD_TIME=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_FS_GENERIC=y
> +CONFIG_OF_EMBED=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_CLK=y
> +CONFIG_DM_ETH=y
> +CONFIG_PCH_GBE=y
> +CONFIG_DM_PCI=y
> +CONFIG_PCI_XILINX=y
> +CONFIG_SYS_NS16550=y
> +CONFIG_LZ4=y
> diff --git a/include/configs/boston.h b/include/configs/boston.h
> new file mode 100644
> index 0000000..b9cc1b9
> --- /dev/null
> +++ b/include/configs/boston.h
> @@ -0,0 +1,69 @@
> +/*
> + * Copyright (C) 2016 Imagination Technologies
> + *
> + * SPDX-License-Identifier:	GPL-2.0
> + */
> +
> +#ifndef __CONFIGS_BOSTON_H__
> +#define __CONFIGS_BOSTON_H__
> +
> +/*
> + * General board configuration
> + */
> +#define CONFIG_BOARD_EARLY_INIT_F
> +#define CONFIG_DISPLAY_BOARDINFO
> +
> +/*
> + * CPU
> + */
> +#define CONFIG_SYS_MIPS_TIMER_FREQ	30000000
> +
> +/*
> + * PCI
> + */
> +#define CONFIG_PCI
> +#define CONFIG_PCI_PNP
> +#define CONFIG_CMD_PCI
> +
> +/*
> + * Environment
> + */
> +#define CONFIG_ENV_IS_NOWHERE
> +#define CONFIG_ENV_SIZE 1024
> +
> +/*
> + * Memory map
> + */
> +#ifdef CONFIG_64BIT
> +# define CONFIG_SYS_SDRAM_BASE		0xffffffff80000000
> +#else
> +# define CONFIG_SYS_SDRAM_BASE		0x80000000
> +#endif
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
> +
> +#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
> +
> +#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x100000)
> +
> +#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0)
> +#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x10000000)
> +
> +#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
> +
> +/*
> + * Console
> + */
> +#define CONFIG_SYS_MAXARGS		16
> +#define CONFIG_SYS_CBSIZE		256
> +#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
> +					 sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_LONGHELP
> +#define CONFIG_BAUDRATE			115200
> +
> +/*
> + * Flash
> + */
> +#define CONFIG_SYS_MAX_FLASH_BANKS	1
> +
> +#endif /* __CONFIGS_BOSTON_H__ */
> 

-- 
- Daniel

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