[U-Boot] [PATCH 2/4] spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock

[Vignesh R]

On Wednesday 27 July 2016 12:05 PM, Jagan Teki wrote:
> On 25 July 2016 at 15:45, Vignesh R <vigneshr at ti.com> wrote:
>> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
>> the driver to use the same.
>>
>> Signed-off-by: Vignesh R <vigneshr at ti.com>
>> ---
>>  drivers/spi/ti_qspi.c | 17 ++++++++++++-----
>>  1 file changed, 12 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
>> index fa7ee229878a..bb72cb03ec24 100644
>> --- a/drivers/spi/ti_qspi.c
>> +++ b/drivers/spi/ti_qspi.c
>> @@ -21,7 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
>>
>>  /* ti qpsi register bit masks */
>>  #define QSPI_TIMEOUT                    2000000
>> -#define QSPI_FCLK                       192000000
>> +#define QSPI_FCLK                      192000000
>> +#define QSPI_DRA7XX_FCLK                76800000
>>  /* clock control */
>>  #define QSPI_CLK_EN                     BIT(31)
>>  #define QSPI_CLK_DIV_MAX                0xffff
>> @@ -101,6 +102,7 @@ struct ti_qspi_priv {
>>  #endif
>>         struct ti_qspi_regs *base;
>>         void *ctrl_mod_mmap;
>> +       ulong fclk;
>>         unsigned int mode;
>>         u32 cmd;
>>         u32 dc;
>> @@ -113,7 +115,7 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
>>         if (!hz)
>>                 clk_div = 0;
>>         else
>> -               clk_div = (QSPI_FCLK / hz) - 1;
>> +               clk_div = (priv->fclk / hz) - 1;
> 
> Then how this relate to max_hz (priv->max_hz), look like it is not
> using anywhere.

I think priv-max_hz defines the max frequency QSPI IP can support (flash
node can always be configured to run at higher or lower frequency which
is specified by spi-max-frequency in flash subnode). What's missing is a
check to see if frequency requested in set_speed() is not greater than
priv->max_hz. I will implement that in another series.


-- 
Regards
Vignesh