[U-Boot] Newbie SPL question for socfpga_sockit

[George Broz]

On 3 March 2016 at 15:07, Marek Vasut <marex at denx.de> wrote:

>> On 3 March 2016 at 14:42, Marek Vasut <marex at denx.de> wrote:
>>> On 03/03/2016 11:27 PM, George Broz wrote:
>>>> Hi Marek,
>>>
>>> Hi!
>>>
>>>> Yes - would love to be using the SPL from 2016.01 for the Terasic board,
>>>> but it does not seem to be working for me with the files from the repo or
>>>> with handoff files I supply & run through qts-filter.sh. This is about two
>>>> layers below where my normal expertise is, so any help getting 2016.01
>>>> (or later) SPL working (with the end goal of having working USB) would
>>>> be much appreciated!
>>>
>>> Are you using sockit ? Which revision (it's etched in the PCB from the
>>> bottom, it's not silkscreen but really part of the copper) ? I'll test
>>> it and get back to you. If I happen to forget about it, remind me ;-)
>>>
>>>> Best regards,
>>>> --George Broz
>>>>
>>>>
>>>> On 3 March 2016 at 14:09, Marek Vasut <marex at denx.de> wrote:
>>>>> On 03/03/2016 11:00 PM, George Broz wrote:
>>>>>> On 3 March 2016 at 06:51, Marek Vasut <marex at denx.de> wrote:
>>>>>>> On 03/03/2016 03:48 PM, Dinh Nguyen wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>> On 03/02/2016 05:24 PM, Marek Vasut wrote:
>>>>>>>>>
>>>>>>>>> Well, that's our usual USB/QSPI cache issue that's tormenting your soul.
>>>>>>>>> CCing Chin ;-)
>>>>>>>>>
>>>>>>>>> Does the issue by any chance magically disappear if you apply this patch:
>>>>>>>>>
>>>>>>>>> diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
>>>>>>>>> index 026e7ef..06802c6 100644
>>>>>>>>> --- a/arch/arm/include/asm/system.h
>>>>>>>>> +++ b/arch/arm/include/asm/system.h
>>>>>>>>> @@ -274,7 +274,7 @@ static inline void set_dacr(unsigned int val)
>>>>>>>>>
>>>>>>>>>  /* options available for data cache on each page */
>>>>>>>>>  enum dcache_option {
>>>>>>>>> -       DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
>>>>>>>>> +       DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) |
>>>>>>>>> TTB_SECT_XN_MASK | TTB_SECT,
>>>>>>>>>         DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
>>>>>>>>>         DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
>>>>>>>>>         DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
>>>>>>>>>
>>>>>>
>>>>>> The 2016.01 code I'm using already includes this patch. If I try
>>>>>> reading a USB stick with dcache on or off
>>>>>> I get the same result:
>>>>>>
>>>>>> => dcache off
>>>>>> => usb reset
>>>>>> resetting USB...
>>>>>> USB0:   Core Release: 2.93a
>>>>>> dwc_otg_core_host_init: Timeout!
>>>>>> dwc_otg_core_host_init: Timeout!
>>>>>> dwc_otg_core_host_init: Timeout!
>>>>>> dwc_otg_core_host_init: Timeout!
>>>>>> dwc_otg_core_host_init: Timeout!
>>>>>> dwc_otg_core_host_init: Timeout!
>>>>>> dwc_otg_core_host_init: Timeout!
>>>>>> dwc_otg_core_host_init: Timeout!
>>>>>> dwc_otg_core_host_init: Timeout!
>>>>>> dwc_otg_core_host_init: Timeout!
>>>>>> dwc_otg_core_host_init: Timeout!
>>>>>> dwc_otg_core_host_init: Timeout!
>>>>>> dwc_otg_core_host_init: Timeout!
>>>>>> dwc_otg_core_host_init: Timeout!
>>>>>> dwc_otg_core_host_init: Timeout!
>>>>>> scanning bus 0 for devices... 1 USB Device(s) found
>>>>>> => usb tree
>>>>>> USB device tree:
>>>>>>   1  Hub (480 Mb/s, 0mA)
>>>>>>       U-Boot Root Hub
>>>>>
>>>>> This more likely means that either clock or reset bits are not
>>>>> configured correctly OR you're using the wrong controller. Since
>>>>> you're mixing old U-Boot SPL with new U-Boot, there can be some
>>>>> discrepancy and I have no idea how to help you with that :(
>>>>>
>>>>>
>>>>> Best regards,
>>>>> Marek Vasut
>>>
>>>
>>> --
>>> Best regards,
>>> Marek Vasut

> On 03/03/2016 11:57 PM, George Broz wrote:
>> Yes - using SocKit, revision D (etching is 10-31212180-D0).
>>
>> Thanks - any help is much appreciated!
>
> Try attached patch.
>

Thanks, Marek. The patch applied cleanly, but the end result is the same

(with DLEVEL=1 in sequencer.c) I get
U-Boot SPL 2016.01 (Mar 03 2016 - 15:28:06)
scc_mgr_initialize:281: Clearing SCC RFILE index 0
scc_mgr_initialize:281: Clearing SCC RFILE index 1
scc_mgr_initialize:281: Clearing SCC RFILE index 2
scc_mgr_initialize:281: Clearing SCC RFILE index 3
scc_mgr_initialize:281: Clearing SCC RFILE index 4
scc_mgr_initialize:281: Clearing SCC RFILE index 5
scc_mgr_initialize:281: Clearing SCC RFILE index 6
scc_mgr_initialize:281: Clearing SCC RFILE index 7
scc_mgr_initialize:281: Clearing SCC RFILE index 8
scc_mgr_initialize:281: Clearing SCC RFILE index 9
scc_mgr_initialize:281: Clearing SCC RFILE index 10
scc_mgr_initialize:281: Clearing SCC RFILE index 11
scc_mgr_initialize:281: Clearing SCC RFILE index 12
scc_mgr_initialize:281: Clearing SCC RFILE index 13
scc_mgr_initialize:281: Clearing SCC RFILE index 14
scc_mgr_initialize:281: Clearing SCC RFILE index 15

4x then hang.



>
>> Best regards,
>> --George
>>


>
> --
> Best regards,
> Marek Vasut