[U-Boot] [PATCH] MIPS: fix mips_cache fallback without __builtin_mips_cache

[Matthew Fortune]

Matthias Schiffer <mschiffer at universe-factory.net> writes:
> >
> > I've disabled the builtin code and compared dissaemblies with and
> without your patch. Without your patch, gcc adds an additional store
> instruction before each cache instruction.
> >
> > E.g. for flush_dcache_range():
> >
> >   18:	afa20008 	sw	v0,8(sp)
> >   1c:	bfb50008 	cache	0x15,8(sp)
> >
> > vs.
> >
> >   14:	bc550000 	cache	0x15,0(v0)
> >
> > The cache operation works anyway, but with your patch better code is
> generated.
> 
> If I understand this correctly, the code without my patch would rather
> invalidate the cache for the address 8(sp), which is part of the stack,
> and not the memory pointed at by v0.

Matthias is correct. These two code sequences will exhibit different
overall behaviour. The latter is much more likely to be what you wanted
from what I can see as the flush is to operate on the value of the
'addr' variable not the address of the addr variable.

The same behaviour could be achieved with:

__asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr));

and

__asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(&addr));

Hope that's useful.

Matthew