[U-Boot] [PATCH 2/4] ARM: DRA7: emif: Fix DDR init sequence during warm reset

[Tom Rini]

On Sat, Mar 05, 2016 at 05:32:29PM +0530, Lokesh Vutla wrote:

> Commit (20fae0a - ARM: DRA7: DDR: Enable SR in Power Management Control)
> enables Self refresh mode by default and during warm reset the EMIF
> contents are preserved. After warm reset EMIF sees that it is idle and
> puts DDR in self-refresh. When in SR, leveling operations cannot be done
> as DDR can only accept SR exit command, so its hanging during warm reset.
> In order to fix this reset the power management control register before
> EMIF initialization if it is a warm reset.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla at ti.com>

Reviewed-by: Tom Rini <trini at konsulko.com>

-- 
Tom
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