[U-Boot] [PATCH] armv8/fsl-lsch2: fix sdhc clock frequency value

[Yangbo Lu]

> -----Original Message-----
> From: york sun
> Sent: Tuesday, March 08, 2016 3:07 AM
> To: Yangbo Lu; u-boot at lists.denx.de
> Subject: Re: [PATCH] armv8/fsl-lsch2: fix sdhc clock frequency value
> 
> On 02/15/2016 07:03 PM, Yangbo Lu wrote:
> > The eSDHC could select to use platform clock or peripheral clock to
> > generate SD clock. The default selection is platform clock. So, fix
> > the clock frequency value that's calculated for eSDHC.
> >
> > Signed-off-by: Yangbo Lu <yangbo.lu at nxp.com>
> > ---
> >  arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> > index 6f6a588..453a93d 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> > @@ -106,9 +106,13 @@ void get_sys_info(struct sys_info *sys_info)
> >  #define HWA_CGA_M2_CLK_SEL	0x00000007
> >  #define HWA_CGA_M2_CLK_SHIFT	0
> >  #ifdef CONFIG_FSL_ESDHC
> > +#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
> >  	rcw_tmp = in_be32(&gur->rcwsr[15]);
> >  	rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
> >  	sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
> > +#else
> > +	sys_info->freq_sdhc = sys_info->freq_systembus; #endif
> >  #endif
> >
> >  #if defined(CONFIG_FSL_IFC)
> >
> 
> Yango,
> 
> The change looks OK. But you didn't define
> CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
> anywhere. Do you have another patch using this macro? So far, this macro
> is only used for T1040QDS and T208xQDS.
> 
> York

[Lu Yangbo-B47093] Hi York. You are right.
Although we don't use this macro presently, we will use it to support SD UHS mode in the future.
Now we could treat it as a bug fix.

Thanks.