[U-Boot] [PATCH 18/69] x86: Create a common header for Intel register access

[Bin Meng]

Hi Simon,

On Mon, Mar 7, 2016 at 10:28 AM, Simon Glass <sjg at chromium.org> wrote:
> There are several blocks of registers that are accessed from all over the
> code on Intel CPUs. These don't currently have their own driver and it is
> not clear whether having a driver makes sense.
>
> An example is the Memory Controller Hub (MCH). We map it to a known location
> on some Intel chips (mostly those without FSP - Firmware Support Package).
>
> Add a new header file for these registers, and move MCH into it.
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
>
>  arch/x86/cpu/ivybridge/cpu.c                      |  1 +
>  arch/x86/cpu/ivybridge/gma.c                      |  1 +
>  arch/x86/cpu/ivybridge/northbridge.c              |  5 +++--
>  arch/x86/cpu/ivybridge/sdram.c                    |  3 ++-
>  arch/x86/include/asm/arch-ivybridge/sandybridge.h |  3 ---
>  arch/x86/include/asm/intel_regs.h                 | 15 +++++++++++++++
>  6 files changed, 22 insertions(+), 6 deletions(-)
>  create mode 100644 arch/x86/include/asm/intel_regs.h
>
> diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
> index c54e800..f847a2f 100644
> --- a/arch/x86/cpu/ivybridge/cpu.c
> +++ b/arch/x86/cpu/ivybridge/cpu.c
> @@ -17,6 +17,7 @@
>  #include <fdtdec.h>
>  #include <pch.h>
>  #include <asm/cpu.h>
> +#include <asm/intel_regs.h>
>  #include <asm/io.h>
>  #include <asm/lapic.h>
>  #include <asm/microcode.h>
> diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
> index 3b6291e..87e06e7 100644
> --- a/arch/x86/cpu/ivybridge/gma.c
> +++ b/arch/x86/cpu/ivybridge/gma.c
> @@ -12,6 +12,7 @@
>  #include <errno.h>
>  #include <fdtdec.h>
>  #include <pci_rom.h>
> +#include <asm/intel_regs.h>
>  #include <asm/io.h>
>  #include <asm/mtrr.h>
>  #include <asm/pci.h>
> diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
> index a066607..f7e0bc3 100644
> --- a/arch/x86/cpu/ivybridge/northbridge.c
> +++ b/arch/x86/cpu/ivybridge/northbridge.c
> @@ -12,6 +12,7 @@
>  #include <asm/msr.h>
>  #include <asm/acpi.h>
>  #include <asm/cpu.h>
> +#include <asm/intel_regs.h>
>  #include <asm/io.h>
>  #include <asm/pci.h>
>  #include <asm/processor.h>
> @@ -167,8 +168,8 @@ static void sandybridge_setup_northbridge_bars(struct udevice *dev)
>         debug("Setting up static registers\n");
>         dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1);
>         dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
> -       dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1);
> -       dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32);
> +       dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1);
> +       dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32);
>         /* 64MB - busses 0-63 */
>         dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
>         dm_pci_write_config32(dev, PCIEXBAR + 4,
> diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
> index e23c422..6f45071 100644
> --- a/arch/x86/cpu/ivybridge/sdram.c
> +++ b/arch/x86/cpu/ivybridge/sdram.c
> @@ -23,6 +23,7 @@
>  #include <asm/processor.h>
>  #include <asm/gpio.h>
>  #include <asm/global_data.h>
> +#include <asm/intel_regs.h>
>  #include <asm/mrccache.h>
>  #include <asm/mtrr.h>
>  #include <asm/pci.h>
> @@ -682,7 +683,7 @@ int dram_init(void)
>  {
>         struct pei_data pei_data __aligned(8) = {
>                 .pei_version = PEI_VERSION,
> -               .mchbar = DEFAULT_MCHBAR,
> +               .mchbar = MCH_BASE_ADDRESS,
>                 .dmibar = DEFAULT_DMIBAR,
>                 .epbar = DEFAULT_EPBAR,
>                 .pciexbar = CONFIG_PCIE_ECAM_BASE,
> diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
> index d137d67..59b05cc 100644
> --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
> +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
> @@ -38,7 +38,6 @@
>  #define IED_SIZE       0x400000
>
>  /* Northbridge BARs */
> -#define DEFAULT_MCHBAR         0xfed10000      /* 16 KB */
>  #define DEFAULT_DMIBAR         0xfed18000      /* 4 KB */
>  #define DEFAULT_EPBAR          0xfed19000      /* 4 KB */
>  #define DEFAULT_RCBABASE       0xfed1c000
> @@ -97,8 +96,6 @@
>  /*
>   * MCHBAR
>   */
> -#define MCHBAR_REG(reg)                (DEFAULT_MCHBAR + (reg))
> -
>  #define SSKPD          0x5d14  /* 16bit (scratchpad) */
>  #define BIOS_RESET_CPL 0x5da8  /* 8bit */
>
> diff --git a/arch/x86/include/asm/intel_regs.h b/arch/x86/include/asm/intel_regs.h
> new file mode 100644
> index 0000000..61e0ec2
> --- /dev/null
> +++ b/arch/x86/include/asm/intel_regs.h
> @@ -0,0 +1,15 @@
> +/*
> + * Copyright (c) 2016 Google, Inc
> + *
> + * SPDX-License-Identifier:    GPL-2.0

nits: GPL-2.0+?

> + */
> +
> +#ifndef __asm_intel_regs_h
> +#define __asm_intel_regs_h

nits: all capital letters

> +
> +/* Access the memory-controller hub */
> +#define MCH_BASE_ADDRESS       0xfed10000
> +#define MCH_BASE_SIZE          0x8000
> +#define MCHBAR_REG(reg)                (MCH_BASE_ADDRESS + (reg))
> +
> +#endif
> --

Reviewed-by: Bin Meng <bmeng.cn at gmail.com>

Regards,
Bin