[U-Boot] [PATCH 45/69] x86: Add an ICH6 pin configuration driver

[Bin Meng]

On Fri, Mar 11, 2016 at 3:17 PM, Bin Meng <bmeng.cn at gmail.com> wrote:
> On Mon, Mar 7, 2016 at 10:28 AM, Simon Glass <sjg at chromium.org> wrote:
>> Add a driver which sets up the pin configuration on x86 devices with an ICH6
>> (or later) Platform Controller Hub.
>>
>> The driver is not in the pinctrl uclass due to some oddities of the way x86
>> devices work:
>>
>> - The GPIO controller is not present in I/O space until it is set up
>> - This is done by writing a register in the PCH
>> - The PCH has a driver which itself uses PCI, another driver
>> - The pinctrl uclass requires that a pinctrl device be available before any
>> other device can be probed
>>
>> It would be possible to work around the limitations by:
>> - Hard-coding the GPIO address rather than reading it from the PCH
>> - Using special x86 PCI access to set the GPIO address in the PCH
>>
>> However it is not clear that this is better, since the pin configuration
>> driver does not actually provide normal pin configuration services - it
>> simply sets up all the pins statically when probed. While this remains the
>> case, it seems better to use a syscon uclass instead. This can be probed
>> whenever it is needed, without any limitations.
>>
>> Also add an 'invert' property to support inverting the input.
>>
>> Signed-off-by: Simon Glass <sjg at chromium.org>
>> ---
>>
>>  arch/x86/include/asm/cpu.h                         |   1 +
>>  arch/x86/lib/Makefile                              |   1 +
>>  arch/x86/lib/pinctrl_ich6.c                        | 216 +++++++++++++++++++++
>>  .../gpio/intel,x86-pinctrl.txt                     |   1 +
>>  4 files changed, 219 insertions(+)
>>  create mode 100644 arch/x86/lib/pinctrl_ich6.c
>>
>
> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>

applied to u-boot-x86/next, thanks!