[U-Boot] [PATCH v2 41/51] x86: broadwell: Add support for SDRAM setup
Simon Glass
sjg at chromium.org
Sat Mar 12 06:07:26 CET 2016
Broadwell uses a binary blob called the memory reference code (MRC) to start
up its SDRAM. This is similar to ivybridge so we can mostly use common code
for running this blob.
Signed-off-by: Simon Glass <sjg at chromium.org>
---
Changes in v2:
- Rename sdram to mrc
arch/x86/cpu/broadwell/Makefile | 1 +
arch/x86/cpu/broadwell/sdram.c | 307 +++++++++++++++++++++++++
arch/x86/include/asm/arch-broadwell/pei_data.h | 177 ++++++++++++++
arch/x86/include/asm/global_data.h | 24 ++
4 files changed, 509 insertions(+)
create mode 100644 arch/x86/cpu/broadwell/sdram.c
create mode 100644 arch/x86/include/asm/arch-broadwell/pei_data.h
diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index 5a62afa..012798f 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -13,3 +13,4 @@ obj-y += pinctrl_broadwell.o
obj-y += power_state.o
obj-y += refcode.o
obj-y += sata.o
+obj-y += sdram.o
diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
new file mode 100644
index 0000000..4bf5d15
--- /dev/null
+++ b/arch/x86/cpu/broadwell/sdram.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * From coreboot src/soc/intel/broadwell/romstage/raminit.c
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pci.h>
+#include <syscon.h>
+#include <asm/cpu.h>
+#include <asm/io.h>
+#include <asm/lpc_common.h>
+#include <asm/mrccache.h>
+#include <asm/mrc_common.h>
+#include <asm/mtrr.h>
+#include <asm/pci.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/me.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/pei_data.h>
+#include <asm/arch/pm.h>
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ return mrc_common_board_get_usable_ram_top(total_size);
+}
+
+void dram_init_banksize(void)
+{
+ mrc_common_dram_init_banksize();
+}
+
+void broadwell_fill_pei_data(struct pei_data *pei_data)
+{
+ pei_data->pei_version = PEI_VERSION;
+ pei_data->board_type = BOARD_TYPE_ULT;
+ pei_data->pciexbar = MCFG_BASE_ADDRESS;
+ pei_data->smbusbar = SMBUS_BASE_ADDRESS;
+ pei_data->ehcibar = EARLY_EHCI_BAR;
+ pei_data->xhcibar = EARLY_XHCI_BAR;
+ pei_data->gttbar = EARLY_GTT_BAR;
+ pei_data->pmbase = ACPI_BASE_ADDRESS;
+ pei_data->gpiobase = GPIO_BASE_ADDRESS;
+ pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE;
+ pei_data->temp_mmio_base = EARLY_TEMP_MMIO;
+ pei_data->tx_byte = sdram_console_tx_byte;
+ pei_data->ddr_refresh_2x = 1;
+}
+
+static inline void pei_data_usb2_port(struct pei_data *pei_data, int port,
+ uint16_t length, uint8_t enable,
+ uint8_t oc_pin, uint8_t location)
+{
+ pei_data->usb2_ports[port].length = length;
+ pei_data->usb2_ports[port].enable = enable;
+ pei_data->usb2_ports[port].oc_pin = oc_pin;
+ pei_data->usb2_ports[port].location = location;
+}
+
+static inline void pei_data_usb3_port(struct pei_data *pei_data, int port,
+ uint8_t enable, uint8_t oc_pin,
+ uint8_t fixed_eq)
+{
+ pei_data->usb3_ports[port].enable = enable;
+ pei_data->usb3_ports[port].oc_pin = oc_pin;
+ pei_data->usb3_ports[port].fixed_eq = fixed_eq;
+}
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ /* DQ byte map for Samus board */
+ const u8 dq_map[2][6][2] = {
+ { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
+ { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
+ { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
+ { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } };
+ /* DQS CPU<>DRAM map for Samus board */
+ const u8 dqs_map[2][8] = {
+ { 2, 0, 1, 3, 6, 4, 7, 5 },
+ { 2, 1, 0, 3, 6, 5, 4, 7 } };
+
+ pei_data->ec_present = 1;
+
+ /* One installed DIMM per channel */
+ pei_data->dimm_channel0_disabled = 2;
+ pei_data->dimm_channel1_disabled = 2;
+
+ memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
+ memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
+
+ /* P0: HOST PORT */
+ pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0,
+ USB_PORT_BACK_PANEL);
+ /* P1: HOST PORT */
+ pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1,
+ USB_PORT_BACK_PANEL);
+ /* P2: RAIDEN */
+ pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
+ USB_PORT_BACK_PANEL);
+ /* P3: SD CARD */
+ pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_INTERNAL);
+ /* P4: RAIDEN */
+ pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP,
+ USB_PORT_BACK_PANEL);
+ /* P5: WWAN (Disabled) */
+ pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
+ USB_PORT_SKIP);
+ /* P6: CAMERA */
+ pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_INTERNAL);
+ /* P7: BT */
+ pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP,
+ USB_PORT_INTERNAL);
+
+ /* P1: HOST PORT */
+ pei_data_usb3_port(pei_data, 0, 1, 0, 0);
+ /* P2: HOST PORT */
+ pei_data_usb3_port(pei_data, 1, 1, 1, 0);
+ /* P3: RAIDEN */
+ pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0);
+ /* P4: RAIDEN */
+ pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0);
+}
+
+static unsigned long get_top_of_ram(struct udevice *dev)
+{
+ /*
+ * Base of DPR is top of usable DRAM below 4GiB. The register has
+ * 1 MiB alignment and reports the TOP of the range, the base
+ * must be calculated from the size in MiB in bits 11:4.
+ */
+ u32 dpr, tom;
+
+ dm_pci_read_config32(dev, DPR, &dpr);
+ tom = dpr & ~((1 << 20) - 1);
+
+ debug("dpt %08x tom %08x\n", dpr, tom);
+ /* Subtract DMA Protected Range size if enabled */
+ if (dpr & DPR_EPM)
+ tom -= (dpr & DPR_SIZE_MASK) << 16;
+
+ return (unsigned long)tom;
+}
+
+/**
+ * sdram_find() - Find available memory
+ *
+ * This is a bit complicated since on x86 there are system memory holes all
+ * over the place. We create a list of available memory blocks
+ *
+ * @dev: Northbridge device
+ */
+static int sdram_find(struct udevice *dev)
+{
+ struct memory_info *info = &gd->arch.meminfo;
+ ulong top_of_ram;
+
+ top_of_ram = get_top_of_ram(dev);
+ mrc_add_memory_area(info, 0, top_of_ram);
+
+ /* Add MTRRs for memory */
+ mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
+
+ return 0;
+}
+
+static int prepare_mrc_cache(struct pei_data *pei_data)
+{
+ struct mrc_data_container *mrc_cache;
+ struct mrc_region entry;
+ int ret;
+
+ ret = mrccache_get_region(NULL, &entry);
+ if (ret)
+ return ret;
+ mrc_cache = mrccache_find_current(&entry);
+ if (!mrc_cache)
+ return -ENOENT;
+
+ pei_data->saved_data = mrc_cache->data;
+ pei_data->saved_data_size = mrc_cache->data_size;
+ debug("%s: at %p, size %x checksum %04x\n", __func__,
+ pei_data->saved_data, pei_data->saved_data_size,
+ mrc_cache->checksum);
+
+ return 0;
+}
+
+int reserve_arch(void)
+{
+ return mrccache_reserve();
+}
+
+int dram_init(void)
+{
+ struct pei_data _pei_data __aligned(8);
+ struct pei_data *pei_data = &_pei_data;
+ struct udevice *dev, *me_dev, *pch_dev;
+ struct chipset_power_state ps;
+ const void *spd_data;
+ int ret, size;
+
+ memset(pei_data, '\0', sizeof(struct pei_data));
+
+ /* Print ME state before MRC */
+ ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
+ if (ret)
+ return ret;
+ intel_me_status(me_dev);
+
+ /* Save ME HSIO version */
+ ret = uclass_first_device(UCLASS_PCH, &pch_dev);
+ if (ret)
+ return ret;
+ if (!pch_dev)
+ return -ENODEV;
+ power_state_get(pch_dev, &ps);
+
+ intel_me_hsio_version(me_dev, &ps.hsio_version, &ps.hsio_checksum);
+
+ broadwell_fill_pei_data(pei_data);
+ mainboard_fill_pei_data(pei_data);
+
+ ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
+ if (ret)
+ return ret;
+ if (!dev)
+ return -ENODEV;
+ size = 256;
+ ret = mrc_locate_spd(dev, size, &spd_data);
+ if (ret)
+ return ret;
+ memcpy(pei_data->spd_data[0][0], spd_data, size);
+ memcpy(pei_data->spd_data[1][0], spd_data, size);
+
+ ret = prepare_mrc_cache(pei_data);
+ if (ret)
+ debug("prepare_mrc_cache failed: %d\n", ret);
+
+ debug("PEI version %#x\n", pei_data->pei_version);
+ ret = mrc_common_init(dev, pei_data, true);
+ if (ret)
+ return ret;
+ debug("Memory init done\n");
+
+ ret = sdram_find(dev);
+ if (ret)
+ return ret;
+ gd->ram_size = gd->arch.meminfo.total_32bit_memory;
+ debug("RAM size %llx\n", (unsigned long long)gd->ram_size);
+
+ debug("MRC output data length %#x at %p\n", pei_data->data_to_save_size,
+ pei_data->data_to_save);
+ /* S3 resume: don't save scrambler seed or MRC data */
+ if (pei_data->boot_mode != SLEEP_STATE_S3) {
+ /*
+ * This will be copied to SDRAM in reserve_arch(), then written
+ * to SPI flash in mrccache_save()
+ */
+ gd->arch.mrc_output = (char *)pei_data->data_to_save;
+ gd->arch.mrc_output_len = pei_data->data_to_save_size;
+ }
+ gd->arch.pei_meminfo = pei_data->meminfo;
+
+ return 0;
+}
+
+/* Use this hook to save our SDRAM parameters */
+int misc_init_r(void)
+{
+ int ret;
+
+ ret = mrccache_save();
+ if (ret)
+ printf("Unable to save MRC data: %d\n", ret);
+ else
+ debug("Saved MRC cache data\n");
+
+ return 0;
+}
+
+void board_debug_uart_init(void)
+{
+ struct udevice *bus = NULL;
+
+ /* com1 / com2 decode range */
+ pci_x86_write_config(bus, PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16);
+
+ pci_x86_write_config(bus, PCH_DEV_LPC, LPC_EN, COMA_LPC_EN,
+ PCI_SIZE_16);
+}
+
+static const struct udevice_id broadwell_syscon_ids[] = {
+ { .compatible = "intel,me", .data = X86_SYSCON_ME },
+ { .compatible = "intel,gma", .data = X86_SYSCON_GMA },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_intel_me) = {
+ .name = "intel_me_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = broadwell_syscon_ids,
+};
diff --git a/arch/x86/include/asm/arch-broadwell/pei_data.h b/arch/x86/include/asm/arch-broadwell/pei_data.h
new file mode 100644
index 0000000..b2cc8b8
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/pei_data.h
@@ -0,0 +1,177 @@
+/*
+ * From Coreboot soc/intel/broadwell/include/soc/pei_data.h
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ASM_ARCH_PEI_DATA_H
+#define ASM_ARCH_PEI_DATA_H
+
+#include <linux/linkage.h>
+
+#define PEI_VERSION 22
+
+typedef void asmlinkage (*tx_byte_func)(unsigned char byte);
+
+enum board_type {
+ BOARD_TYPE_CRB_MOBILE = 0, /* CRB Mobile */
+ BOARD_TYPE_CRB_DESKTOP, /* CRB Desktop */
+ BOARD_TYPE_USER1, /* SV mobile */
+ BOARD_TYPE_USER2, /* SV desktop */
+ BOARD_TYPE_USER3, /* SV server */
+ BOARD_TYPE_ULT, /* ULT */
+ BOARD_TYPE_CRB_EMBDEDDED, /* CRB Embedded */
+ BOARD_TYPE_UNKNOWN,
+};
+
+#define MAX_USB2_PORTS 14
+#define MAX_USB3_PORTS 6
+#define USB_OC_PIN_SKIP 8
+
+enum usb2_port_location {
+ USB_PORT_BACK_PANEL = 0,
+ USB_PORT_FRONT_PANEL,
+ USB_PORT_DOCK,
+ USB_PORT_MINI_PCIE,
+ USB_PORT_FLEX,
+ USB_PORT_INTERNAL,
+ USB_PORT_SKIP,
+ USB_PORT_NGFF_DEVICE_DOWN,
+};
+
+struct usb2_port_setting {
+ /*
+ * Usb Port Length:
+ * [16:4] = length in inches in octal format
+ * [3:0] = decimal point
+ */
+ uint16_t length;
+ uint8_t enable;
+ uint8_t oc_pin;
+ uint8_t location;
+} __packed;
+
+struct usb3_port_setting {
+ uint8_t enable;
+ uint8_t oc_pin;
+ /*
+ * Set to 0 if trace length is > 5 inches
+ * Set to 1 if trace length is <= 5 inches
+ */
+ uint8_t fixed_eq;
+} __packed;
+
+
+struct pei_data {
+ uint32_t pei_version;
+
+ enum board_type board_type;
+ int boot_mode;
+ int ec_present;
+ int usbdebug;
+
+ /* Base addresses */
+ uint32_t pciexbar;
+ uint16_t smbusbar;
+ uint32_t xhcibar;
+ uint32_t ehcibar;
+ uint32_t gttbar;
+ uint32_t rcba;
+ uint32_t pmbase;
+ uint32_t gpiobase;
+ uint32_t temp_mmio_base;
+ uint32_t tseg_size;
+
+ /*
+ * 0 = leave channel enabled
+ * 1 = disable dimm 0 on channel
+ * 2 = disable dimm 1 on channel
+ * 3 = disable dimm 0+1 on channel
+ */
+ int dimm_channel0_disabled;
+ int dimm_channel1_disabled;
+ /* Set to 0 for memory down */
+ uint8_t spd_addresses[4];
+ /* Enable 2x Refresh Mode */
+ int ddr_refresh_2x;
+ /* DQ pins are interleaved on board */
+ int dq_pins_interleaved;
+ /* Limit DDR3 frequency */
+ int max_ddr3_freq;
+ /* Disable self refresh */
+ int disable_self_refresh;
+ /* Disable cmd power/CKEPD */
+ int disable_cmd_pwr;
+
+ /* USB port configuration */
+ struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
+ struct usb3_port_setting usb3_ports[MAX_USB3_PORTS];
+
+ /*
+ * USB3 board specific PHY tuning
+ */
+
+ /* Valid range: 0x69 - 0x80 */
+ uint8_t usb3_txout_volt_dn_amp_adj[MAX_USB3_PORTS];
+ /* Valid range: 0x80 - 0x9c */
+ uint8_t usb3_txout_imp_sc_volt_amp_adj[MAX_USB3_PORTS];
+ /* Valid range: 0x39 - 0x80 */
+ uint8_t usb3_txout_de_emp_adj[MAX_USB3_PORTS];
+ /* Valid range: 0x3d - 0x4a */
+ uint8_t usb3_txout_imp_adj_volt_amp[MAX_USB3_PORTS];
+
+ /* Console output function */
+ tx_byte_func tx_byte;
+
+ /*
+ * DIMM SPD data for memory down configurations
+ * [CHANNEL][SLOT][SPD]
+ */
+ uint8_t spd_data[2][2][512];
+
+ /*
+ * LPDDR3 DQ byte map
+ * [CHANNEL][ITERATION][2]
+ *
+ * Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side)
+ * DQByteMap[0] - ClkDQByteMap:
+ * - If clock is per rank, program to [0xFF, 0xFF]
+ * - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
+ * - If clock is shared by 2 ranks but does not go to all bytes,
+ * Entry[i] defines which DQ bytes Group i services
+ * DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB
+ * DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB
+ * DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB
+ * For DDR, DQByteMap[3:1] = [0xFF, 0]
+ * DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0]
+ * since we have 1 CTL / rank
+ * DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0]
+ * since we have 1 CA Vref
+ */
+ uint8_t dq_map[2][6][2];
+
+ /*
+ * LPDDR3 Map from CPU DQS pins to SDRAM DQS pins
+ * [CHANNEL][MAX_BYTES]
+ */
+ uint8_t dqs_map[2][8];
+
+ /* Data read from flash and passed into MRC */
+ const void *saved_data;
+ int saved_data_size;
+
+ /* Disable use of saved data (can be set by mainboard) */
+ int disable_saved_data;
+
+ /* Data from MRC that should be saved to flash */
+ void *data_to_save;
+ int data_to_save_size;
+ struct pei_memory_info meminfo;
+} __packed;
+
+void mainboard_fill_pei_data(struct pei_data *pei_data);
+void broadwell_fill_pei_data(struct pei_data *pei_data);
+
+#endif
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 0ca518c..3bc2ac2 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -19,6 +19,29 @@ enum pei_boot_mode_t {
};
+struct dimm_info {
+ uint32_t dimm_size;
+ uint16_t ddr_type;
+ uint16_t ddr_frequency;
+ uint8_t rank_per_dimm;
+ uint8_t channel_num;
+ uint8_t dimm_num;
+ uint8_t bank_locator;
+ /* The 5th byte is '\0' for the end of string */
+ uint8_t serial[5];
+ /* The 19th byte is '\0' for the end of string */
+ uint8_t module_part_number[19];
+ uint16_t mod_id;
+ uint8_t mod_type;
+ uint8_t bus_width;
+} __packed;
+
+struct pei_memory_info {
+ uint8_t dimm_cnt;
+ /* Maximum num of dimm is 8 */
+ struct dimm_info dimm[8];
+} __packed;
+
struct memory_area {
uint64_t start;
uint64_t size;
@@ -59,6 +82,7 @@ struct arch_global_data {
enum pei_boot_mode_t pei_boot_mode;
const struct pch_gpio_map *gpio_map; /* board GPIO map */
struct memory_info meminfo; /* Memory information */
+ struct pei_memory_info pei_meminfo; /* PEI memory information */
#ifdef CONFIG_HAVE_FSP
void *hob_list; /* FSP HOB list */
#endif
--
2.7.0.rc3.207.g0ac5344
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