[U-Boot] [PATCH v3 06/10] x86: dts: Drop memory SPD compatible string

[Simon Glass]

This is not needed now that the memory controller driver has the SPD data
in its own node.

Signed-off-by: Simon Glass <sjg at chromium.org>
Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/dts/chromebook_link.dts | 1 -
 include/fdtdec.h                 | 1 -
 lib/fdtdec.c                     | 1 -
 3 files changed, 3 deletions(-)

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index a424f6b..fb1b31d 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -233,7 +233,6 @@
 					<&gpio_b 11 0>, <&gpio_a 10 0>;
 			u-boot,dm-pre-reloc;
 			spd {
-				compatible = "memory-spd";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				elpida_4Gb_1600_x16 {
diff --git a/include/fdtdec.h b/include/fdtdec.h
index f87b5da..fb88273 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -152,7 +152,6 @@ enum fdt_compat_id {
 	COMPAT_SAMSUNG_EXYNOS5_I2C,	/* Exynos5 High Speed I2C Controller */
 	COMPAT_SAMSUNG_EXYNOS_SYSMMU,	/* Exynos sysmmu */
 	COMPAT_INTEL_MICROCODE,		/* Intel microcode update */
-	COMPAT_MEMORY_SPD,		/* Memory SPD information */
 	COMPAT_INTEL_PANTHERPOINT_AHCI,	/* Intel Pantherpoint AHCI */
 	COMPAT_INTEL_MODEL_206AX,	/* Intel Model 206AX CPU */
 	COMPAT_INTEL_GMA,		/* Intel Graphics Media Accelerator */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index ddbd1ae..70acc29 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -57,7 +57,6 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(SAMSUNG_EXYNOS5_I2C, "samsung,exynos5-hsi2c"),
 	COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
 	COMPAT(INTEL_MICROCODE, "intel,microcode"),
-	COMPAT(MEMORY_SPD, "memory-spd"),
 	COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"),
 	COMPAT(INTEL_MODEL_206AX, "intel,model-206ax"),
 	COMPAT(INTEL_GMA, "intel,gma"),
-- 
2.7.0.rc3.207.g0ac5344