[U-Boot] Please pull u-boot-x86
Bin Meng
bmeng.cn at gmail.com
Thu Mar 17 03:31:48 CET 2016
Hi Tom,
The following changes since commit f8a4826383860318d90079bf40402447d369ad87:
spl: arm: Make sure to include all of the u_boot_list entries
(2016-03-16 15:27:55 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-x86.git master
for you to fetch changes up to 82ceba2ca2487c4967419cf7053e1301709219e5:
x86: Add congatec conga-QA3/E3845-4G (Bay Trail) support (2016-03-17
10:27:27 +0800)
----------------------------------------------------------------
Bin Meng (12):
x86: Move asm/arch-coreboot/tables.h to a common place
x86: Move sysinfo related to sysinfo.h
x86: Clean up coreboot_tables.h
x86: Change to use start/end address pair in write_tables()
x86: Use a macro for ROM table alignment
x86: Change write_acpi_tables() signature a little bit
x86: Simplify codes in write_tables()
x86: Support writing configuration tables in high area
x86: Implement functions for writing coreboot table
x86: Support booting SeaBIOS
x86: qemu: Enable ACPI table generation by default
x86: Document how to play with SeaBIOS
Simon Glass (69):
video: Allow simple-panel to be used without regulators
cpu: Add support for microcode version and CPU ID
gpio: Add a function to obtain a GPIO vector value
gpio: Use const where possible
pci: Add functions to update PCI configuration registers
pci: Correct a few comments and nits
malloc_simple: Add a little more debugging
x86: cpu: Make the vendor table const
x86: Add some more common MSR indexes
x86: link: Add required GPIO properties
x86: dts: link: Move SPD info into the memory controller
x86: dts: link: Add board ID GPIOs
x86: gpio: Correct GPIO setup ordering
x86: Add a script to aid code conversion from coreboot
x86: Correct duplicate POST values
x86: Tidy up mp_init to reduce duplication
x86: Add comments to the SIPI vector
x86: broadwell: Add a few microcode files
dm: timer: Correct timer init ordering after relocation
syscon: Avoid returning a device on failure
input: i8042: Make sure the keyboard is enabled
x86: Allow use of serial soon after relocation
x86: cpu: Add functions to return the family and stepping
x86: Move cache-as-RAM code into a common location
x86: Move microcode code to a common location
x86: Create a common header for Intel register access
x86: Add the root-complex block to common intel registers
x86: Move common LPC code to its own place
x86: Move common CPU code to its own place
x86: Rename PORT_RESET to IO_PORT_RESET
x86: Move Intel Management Engine code to a common place
x86: ivybridge: Drop sandybridge_early_init()
x86: Add macros to clear and set I/O bits
x86: Allow I/O functions to use pointers
x86: Move common MRC Kconfig options to the common file
x86: Record the CPU details when starting each core
x86: ivybridge: Show microcode version for each core
x86: Update microcode for secondary CPUs
x86: link: Add pin configuration to the device tree
x86: Add an ICH6 pin configuration driver
x86: gpio: Allow the pinctrl driver to set up the pin config
x86: Drop all the old pin configuration code
x86: Add support for running Intel reference code
x86: dts: Update the pinctrl binding a little
x86: Add basic support for broadwell
x86: broadwell: Add a PCH driver
x86: broadwell: Add a pinctrl driver
x86: broadwell: Add a SATA driver
x86: broadwell: Add a northbridge driver
x86: broadwell: Add an LPC driver
x86: broadwell: Add reference code support
x86: broadwell: Add power-control support
x86: broadwell: Add support for SDRAM setup
x86: broadwell: Add a GPIO driver
x86: broadwell: Add support for high-speed I/O lane with ME
x86: broadwell: Add video support
x86: Add a default address for reference code
x86: Use white on black for the console on chromebooks
x86: Update README for new developments
x86: Add a function to set the IOAPIC ID
x86: Fix a header nit in x86-chromebook.h
arm: Add a 64-bit division routine to the private library
dhry: Correct dhrystone calculation for fast machines
x86: Move common PCH code into a common place
x86: Add common SDRAM-init code
x86: ivybridge: Convert to use the common SDRAM code
x86: dts: Drop memory SPD compatible string
x86: Support a chained-boot development flow
x86: Add support for the samus chromebook
Stefan Roese (1):
x86: Add congatec conga-QA3/E3845-4G (Bay Trail) support
Makefile
| 14 +-
arch/arm/lib/Makefile
| 3 +-
arch/arm/lib/_uldivmod.S
| 245 +++++++++++
arch/x86/Kconfig
| 87 ++++
arch/x86/cpu/Makefile | 2 +
arch/x86/cpu/broadwell/Kconfig
| 30 ++
arch/x86/cpu/broadwell/Makefile | 17 +
arch/x86/cpu/broadwell/cpu.c
| 761 +++++++++++++++++++++++++++++++++
arch/x86/cpu/broadwell/iobp.c
| 144 +++++++
arch/x86/cpu/broadwell/lpc.c
| 77 ++++
arch/x86/cpu/broadwell/me.c
| 57 +++
arch/x86/cpu/broadwell/northbridge.c
| 59 +++
arch/x86/cpu/broadwell/pch.c
| 540 +++++++++++++++++++++++
arch/x86/cpu/broadwell/pinctrl_broadwell.c
| 278 ++++++++++++
arch/x86/cpu/broadwell/power_state.c
| 90 ++++
arch/x86/cpu/broadwell/refcode.c
| 113 +++++
arch/x86/cpu/broadwell/sata.c
| 269 ++++++++++++
arch/x86/cpu/broadwell/sdram.c
| 307 +++++++++++++
arch/x86/cpu/coreboot/sdram.c | 1 -
arch/x86/cpu/coreboot/tables.c | 1 -
arch/x86/cpu/cpu.c
| 17 +-
arch/x86/cpu/intel_common/Makefile | 16 +
arch/x86/cpu/{ivybridge => intel_common}/car.S
| 4 +-
arch/x86/cpu/intel_common/cpu.c
| 111 +++++
arch/x86/cpu/intel_common/lpc.c
| 100 +++++
arch/x86/cpu/{ivybridge => intel_common}/me_status.c
| 20 +-
arch/x86/cpu/{ivybridge/microcode_intel.c =>
intel_common/microcode.c} | 11 +-
arch/x86/cpu/intel_common/mrc.c
| 271 ++++++++++++
arch/x86/cpu/intel_common/pch.c
| 25 ++
arch/x86/cpu/{ivybridge => intel_common}/report_platform.c
| 2 +-
arch/x86/cpu/ioapic.c | 16 +
arch/x86/cpu/ivybridge/Kconfig
| 27 +-
arch/x86/cpu/ivybridge/Makefile | 4 -
arch/x86/cpu/ivybridge/bd82x6x.c
| 17 +-
arch/x86/cpu/ivybridge/cpu.c
| 84 +---
arch/x86/cpu/ivybridge/early_me.c
| 31 +-
arch/x86/cpu/ivybridge/gma.c | 1 +
arch/x86/cpu/ivybridge/lpc.c
| 77 +---
arch/x86/cpu/ivybridge/model_206ax.c
| 8 +-
arch/x86/cpu/ivybridge/northbridge.c
| 5 +-
arch/x86/cpu/ivybridge/sata.c
| 47 +-
arch/x86/cpu/ivybridge/sdram.c
| 400 ++++-------------
arch/x86/cpu/mp_init.c
| 90 ++--
arch/x86/cpu/qemu/fw_cfg.c
| 5 +-
arch/x86/cpu/sipi_vector.S | 1 +
arch/x86/cpu/start.S
| 80 ++++
arch/x86/dts/Makefile | 2 +
arch/x86/dts/chromebook_link.dts
| 383 ++++++++++++-----
arch/x86/dts/chromebook_samus.dts
| 628 +++++++++++++++++++++++++++
arch/x86/dts/conga-qeval20-qa3-e3845.dts
| 278 ++++++++++++
arch/x86/dts/microcode/m7240651_0000001c.dtsi
| 1328 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
arch/x86/dts/microcode/mc0306d4_00000018.dtsi
| 944 ++++++++++++++++++++++++++++++++++++++++
arch/x86/include/asm/acpi_table.h
| 2 +-
arch/x86/include/asm/arch-broadwell/cpu.h
| 48 +++
arch/x86/include/asm/arch-broadwell/gpio.h
| 91 ++++
arch/x86/include/asm/arch-broadwell/iomap.h
| 53 +++
arch/x86/include/asm/arch-broadwell/lpc.h
| 32 ++
arch/x86/include/asm/arch-broadwell/me.h
| 200 +++++++++
arch/x86/include/asm/arch-broadwell/pch.h
| 153 +++++++
arch/x86/include/asm/arch-broadwell/pei_data.h
| 177 ++++++++
arch/x86/include/asm/arch-broadwell/pm.h
| 129 ++++++
arch/x86/include/asm/arch-broadwell/rcb.h
| 58 +++
arch/x86/include/asm/arch-broadwell/spi.h
| 87 ++++
arch/x86/include/asm/arch-coreboot/sysinfo.h
| 4 +-
arch/x86/include/asm/arch-ivybridge/me.h
| 333 +--------------
arch/x86/include/asm/arch-ivybridge/model_206ax.h | 17 -
arch/x86/include/asm/arch-ivybridge/pch.h
| 62 ---
arch/x86/include/asm/arch-ivybridge/sandybridge.h | 7 -
arch/x86/include/asm/{arch-coreboot/tables.h => coreboot_tables.h}
| 167 ++++----
arch/x86/include/asm/cpu.h
| 27 ++
arch/x86/include/asm/cpu_common.h
| 35 ++
arch/x86/include/asm/global_data.h
| 24 ++
arch/x86/include/asm/gpio.h
| 138 +-----
arch/x86/include/asm/intel_regs.h
| 28 ++
arch/x86/include/asm/io.h
| 34 +-
arch/x86/include/asm/ioapic.h | 2 +
arch/x86/include/asm/lpc_common.h
| 59 +++
arch/x86/include/asm/me_common.h
| 373 ++++++++++++++++
arch/x86/include/asm/{arch-ivybridge => }/microcode.h | 12 +
arch/x86/include/asm/mrc_common.h
| 55 +++
arch/x86/include/asm/msr-index.h
| 41 +-
arch/x86/include/asm/pch_common.h
| 56 +++
arch/x86/include/asm/post.h
| 4 +-
arch/x86/include/asm/processor.h
| 2 +-
arch/x86/include/asm/report_platform.h | 19 +
arch/x86/include/asm/sipi.h | 1 +
arch/x86/include/asm/tables.h | 5 +
arch/x86/lib/Makefile | 2 +
arch/x86/lib/acpi_table.c
| 4 +-
arch/x86/lib/coreboot_table.c
| 136 ++++++
arch/x86/lib/fsp/fsp_car.S | 2 +
arch/x86/lib/pinctrl_ich6.c
| 216 ++++++++++
arch/x86/lib/tables.c
| 77 +++-
board/congatec/Kconfig
| 29 ++
board/congatec/conga-qeval20-qa3-e3845/Kconfig
| 28 ++
board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS | 7 +
board/congatec/conga-qeval20-qa3-e3845/Makefile | 7 +
board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
| 31 ++
board/congatec/conga-qeval20-qa3-e3845/start.S | 9 +
board/coreboot/coreboot/coreboot.c | 5 -
board/efi/efi-x86/efi.c | 5 -
board/google/Kconfig | 13 +
board/google/chromebook_link/link.c
| 138 ------
board/google/chromebook_samus/Kconfig
| 40 ++
board/google/chromebook_samus/MAINTAINERS | 6 +
board/google/chromebook_samus/Makefile | 7 +
board/google/chromebook_samus/samus.c | 18 +
board/google/chromebox_panther/panther.c | 4 -
board/intel/bayleybay/bayleybay.c | 5 -
board/intel/cougarcanyon2/cougarcanyon2.c
| 6 +-
board/intel/crownbay/crownbay.c | 5 -
board/intel/galileo/galileo.c | 5 -
board/intel/minnowmax/minnowmax.c | 8 -
cmd/cpu.c | 7 +
common/board_f.c | 7 +
common/board_r.c
| 4 +-
common/malloc_simple.c
| 7 +-
configs/bayleybay_defconfig | 2 +
configs/chromebook_samus_defconfig
| 51 +++
configs/conga-qeval20-qa3-e3845_defconfig
| 47 ++
configs/cougarcanyon2_defconfig | 2 +
configs/crownbay_defconfig | 2 +
configs/galileo_defconfig | 2 +
configs/minnowmax_defconfig | 2 +
configs/qemu-x86_defconfig | 1 +
doc/README.x86
| 163 ++++++-
doc/device-tree-bindings/gpio/intel,x86-broadwell-pinctrl.txt
| 208 +++++++++
doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
| 22 +-
drivers/core/syscon-uclass.c | 1 +
drivers/gpio/Kconfig | 9 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-uclass.c
| 26 +-
drivers/gpio/intel_broadwell_gpio.c
| 198 +++++++++
drivers/gpio/intel_ich6_gpio.c
| 191 +--------
drivers/input/i8042.c | 4 +
drivers/pci/pci-uclass.c
| 58 ++-
drivers/serial/serial-uclass.c
| 2 +-
drivers/video/Kconfig
| 14 +-
drivers/video/Makefile | 2 +
drivers/video/broadwell_igd.c
| 797 ++++++++++++++++++++++++++++++++++
drivers/video/coreboot_fb.c | 1 -
drivers/video/i915_reg.h
| 362 ++++++++++++++++
drivers/video/simple_panel.c
| 18 +-
include/asm-generic/gpio.h
| 20 +-
include/configs/chromebook_samus.h
| 29 ++
include/configs/conga-qeval20-qa3-e3845.h
| 65 +++
include/configs/x86-chromebook.h
| 8 +-
include/cpu.h | 5 +
include/dt-bindings/gpio/x86-gpio.h | 12 +
include/fdtdec.h | 2 -
include/i8042.h | 1 +
include/pci.h
| 29 +-
lib/dhry/cmd_dhry.c
| 8 +-
lib/fdtdec.c | 2 -
scripts/coreboot.sed | 17 +
155 files changed, 12061 insertions(+), 1824 deletions(-)
create mode 100644 arch/arm/lib/_uldivmod.S
create mode 100644 arch/x86/cpu/broadwell/Kconfig
create mode 100644 arch/x86/cpu/broadwell/Makefile
create mode 100644 arch/x86/cpu/broadwell/cpu.c
create mode 100644 arch/x86/cpu/broadwell/iobp.c
create mode 100644 arch/x86/cpu/broadwell/lpc.c
create mode 100644 arch/x86/cpu/broadwell/me.c
create mode 100644 arch/x86/cpu/broadwell/northbridge.c
create mode 100644 arch/x86/cpu/broadwell/pch.c
create mode 100644 arch/x86/cpu/broadwell/pinctrl_broadwell.c
create mode 100644 arch/x86/cpu/broadwell/power_state.c
create mode 100644 arch/x86/cpu/broadwell/refcode.c
create mode 100644 arch/x86/cpu/broadwell/sata.c
create mode 100644 arch/x86/cpu/broadwell/sdram.c
create mode 100644 arch/x86/cpu/intel_common/Makefile
rename arch/x86/cpu/{ivybridge => intel_common}/car.S (98%)
create mode 100644 arch/x86/cpu/intel_common/cpu.c
create mode 100644 arch/x86/cpu/intel_common/lpc.c
rename arch/x86/cpu/{ivybridge => intel_common}/me_status.c (93%)
rename arch/x86/cpu/{ivybridge/microcode_intel.c =>
intel_common/microcode.c} (96%)
create mode 100644 arch/x86/cpu/intel_common/mrc.c
create mode 100644 arch/x86/cpu/intel_common/pch.c
rename arch/x86/cpu/{ivybridge => intel_common}/report_platform.c (98%)
create mode 100644 arch/x86/dts/chromebook_samus.dts
create mode 100644 arch/x86/dts/conga-qeval20-qa3-e3845.dts
create mode 100644 arch/x86/dts/microcode/m7240651_0000001c.dtsi
create mode 100644 arch/x86/dts/microcode/mc0306d4_00000018.dtsi
create mode 100644 arch/x86/include/asm/arch-broadwell/cpu.h
create mode 100644 arch/x86/include/asm/arch-broadwell/gpio.h
create mode 100644 arch/x86/include/asm/arch-broadwell/iomap.h
create mode 100644 arch/x86/include/asm/arch-broadwell/lpc.h
create mode 100644 arch/x86/include/asm/arch-broadwell/me.h
create mode 100644 arch/x86/include/asm/arch-broadwell/pch.h
create mode 100644 arch/x86/include/asm/arch-broadwell/pei_data.h
create mode 100644 arch/x86/include/asm/arch-broadwell/pm.h
create mode 100644 arch/x86/include/asm/arch-broadwell/rcb.h
create mode 100644 arch/x86/include/asm/arch-broadwell/spi.h
rename arch/x86/include/asm/{arch-coreboot/tables.h => coreboot_tables.h} (53%)
create mode 100644 arch/x86/include/asm/cpu_common.h
create mode 100644 arch/x86/include/asm/intel_regs.h
create mode 100644 arch/x86/include/asm/lpc_common.h
create mode 100644 arch/x86/include/asm/me_common.h
rename arch/x86/include/asm/{arch-ivybridge => }/microcode.h (63%)
create mode 100644 arch/x86/include/asm/mrc_common.h
create mode 100644 arch/x86/include/asm/pch_common.h
create mode 100644 arch/x86/include/asm/report_platform.h
create mode 100644 arch/x86/lib/coreboot_table.c
create mode 100644 arch/x86/lib/pinctrl_ich6.c
create mode 100644 board/congatec/Kconfig
create mode 100644 board/congatec/conga-qeval20-qa3-e3845/Kconfig
create mode 100644 board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS
create mode 100644 board/congatec/conga-qeval20-qa3-e3845/Makefile
create mode 100644 board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
create mode 100644 board/congatec/conga-qeval20-qa3-e3845/start.S
create mode 100644 board/google/chromebook_samus/Kconfig
create mode 100644 board/google/chromebook_samus/MAINTAINERS
create mode 100644 board/google/chromebook_samus/Makefile
create mode 100644 board/google/chromebook_samus/samus.c
create mode 100644 configs/chromebook_samus_defconfig
create mode 100644 configs/conga-qeval20-qa3-e3845_defconfig
create mode 100644
doc/device-tree-bindings/gpio/intel,x86-broadwell-pinctrl.txt
create mode 100644 drivers/gpio/intel_broadwell_gpio.c
create mode 100644 drivers/video/broadwell_igd.c
create mode 100644 drivers/video/i915_reg.h
create mode 100644 include/configs/chromebook_samus.h
create mode 100644 include/configs/conga-qeval20-qa3-e3845.h
create mode 100644 scripts/coreboot.sed
Regards,
Bin
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