[U-Boot] [PATCH v4 11/14] crypto/fsl: Make CAAM transactions cacheable

[york sun]

On 02/08/2016 09:27 PM, Saksham Jain wrote:
> To solve CAAM coherency issue on ls2080a and ls2085a.
> When Caches are enabled and CAAM's DMA's AXI transcations are not
> made cacheable, Core reads/write data from/to Caches and CAAM does from
> Main Memory. This forces data flushes to synchronize various data structures
> But even if any data in proximity of these structures is read by core,
> these structures again are fetched in caches.
> 
> To avoid this problem, either all the data that CAAM accesses can be made
> cache line aligned or CAAM transcations can be made cacheable.
> 
> So, this commit makes CAAM transcations as Write Back with Write and Read
> Allocate.
> 

Please keep line wrap under 72 characters and keep it consistent.

York