[U-Boot] [PATCH 9/9][v2] armv8: ls1012a: Add support of ls1012ardb board

[York Sun]

On 05/11/2016 12:30 AM, Prabhakar Kushwaha wrote:
> QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
> development platform, with a complete debugging environment.
> The LS1012ARDB board supports the QorIQ LS1012A processor and is
> optimized to support the high-bandwidth DDR3L memory and
> a full complement of high-speed SerDes ports.
> 
> Signed-off-by: Calvin Johnson <calvin.johnson at nxp.com>
> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava at nxp.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
> ---
> Changes for v2: Sending as it is
> 
>  arch/arm/Kconfig                        |  10 ++
>  arch/arm/dts/Makefile                   |   3 +-
>  arch/arm/dts/fsl-ls1012a-rdb.dts        |  16 +++
>  arch/arm/dts/fsl-ls1012a-rdb.dtsi       |  39 ++++++
>  board/freescale/ls1012ardb/Kconfig      |  15 +++
>  board/freescale/ls1012ardb/MAINTAINERS  |   6 +
>  board/freescale/ls1012ardb/Makefile     |   7 ++
>  board/freescale/ls1012ardb/README       |  89 ++++++++++++++
>  board/freescale/ls1012ardb/ls1012ardb.c | 210 ++++++++++++++++++++++++++++++++
>  configs/ls1012ardb_qspi_defconfig       |  32 +++++
>  include/configs/ls1012ardb.h            |  59 +++++++++
>  11 files changed, 485 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dts
>  create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dtsi
>  create mode 100644 board/freescale/ls1012ardb/Kconfig
>  create mode 100644 board/freescale/ls1012ardb/MAINTAINERS
>  create mode 100644 board/freescale/ls1012ardb/Makefile
>  create mode 100644 board/freescale/ls1012ardb/README
>  create mode 100644 board/freescale/ls1012ardb/ls1012ardb.c
>  create mode 100644 configs/ls1012ardb_qspi_defconfig
>  create mode 100644 include/configs/ls1012ardb.h
> 

<snip>

> diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS
> new file mode 100644
> index 0000000..757e810
> --- /dev/null
> +++ b/board/freescale/ls1012ardb/MAINTAINERS
> @@ -0,0 +1,6 @@
> +LS1012ARDB BOARD
> +M:
> +S:	Maintained
> +F:	board/freescale/ls1012ardb/
> +F:	include/configs/ls1012ardb.h
> +F:	configs/ls1012ardb_defconfig

Who is the maintainer for this board?

> diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
> new file mode 100644
> index 0000000..05fa9d9
> --- /dev/null
> +++ b/board/freescale/ls1012ardb/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Copyright 2016 Freescale Semiconductor, Inc.
> +#
> +# SPDX-License-Identifier:      GPL-2.0+
> +#
> +
> +obj-y += ls1012ardb.o
> diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README
> new file mode 100644
> index 0000000..cda03f6
> --- /dev/null
> +++ b/board/freescale/ls1012ardb/README
> @@ -0,0 +1,89 @@
> +Overview
> +--------
> +The LS1012ARDB power supplies (PS) provide all the voltages necessary
> +for the correct operation of the LS1012A processor, DDR3L, QSPI memory,
> +and other onboard peripherals.
> +
> +LS1012A SoC Overview
> +--------------------
> +The LS1012A features an advanced 64-bit ARM v8 Cortex-
> +A53 processor, with 32 KB of parity protected L1-I cache,
> +32 KB of ECC protected L1-D cache, as well as 256 KB of
> +ECC protected L2 cache.
> +
> +The LS1012A SoC includes the following function and features:
> + - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
> + - ARM v8 cryptography extensions
> + - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
> +    16-/8-bit operation (no ECC support)
> + - ARM core-link CCI-400 cache coherent interconnect
> + - Packet Forwarding Engine (PFE)
> + - Cryptography acceleration (SEC)
> + - Ethernet interfaces supported by PFE:
> + - One Configurable x3 SerDes:
> +    Two Serdes PLLs supported for usage by any SerDes data lane
> +    Support for up to 6 GBaud operation
> + - High-speed peripheral interfaces:
> +     - One PCI Express Gen2 controller, supporting x1 operation
> +     - One serial ATA (SATA Gen 3.0) controller
> +     - One USB 3.0/2.0 controller with integrated PHY
> +     - One USB 2.0 controller with ULPI interface. .
> + - Additional peripheral interfaces:
> +    - One quad serial peripheral interface (QuadSPI) controller
> +    - One serial peripheral interface (SPI) controller
> +    - Two enhanced secure digital host controllers
> +    - Two I2C controllers
> +    - One 16550 compliant DUART (two UART interfaces)
> +    - Two general purpose IOs (GPIO)
> +    - Two FlexTimers
> +    - Five synchronous audio interfaces (SAI)
> +    - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
> +    - Single-source clocking solution enabling generation of core, platform,
> +    DDR, SerDes, and USB clocks from a single external crystal and internal
> +    crystaloscillator
> +    - Thermal monitor unit (TMU) with +/- 3C accuracy
> +    - Two WatchDog timers
> +    - ARM generic timer
> + - QorIQ platform's trust architecture 2.1

SoC overview should be put into a common file for SoC. Please add technical
information into README. This is not a product brochure.

> +
> + LS1012ARDB board Overview
> + -----------------------
> + - SERDES Connections, 4 lanes supporting:
> +      - PCI Express - 3.0
> +      - SGMII, SGMII 2.5
> +      - SATA 3.0
> + - DDR Controller
> +     - 6-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s

Obviously this is a copy-n-paste. I guess you meant 16-bit. I am going to stop
here. Check my comments for qds patch.

York