[U-Boot] [GIT PULL v2] Xilinx changes
Michal Simek
monstr at monstr.eu
Tue May 24 13:36:42 CEST 2016
Hi Tom,
here are patches I have collected. I expect some others changes will
come after that.
I have fixed one MB compilation issue in v2 (just missing one variable).
Sorry for that.
Thanks,
Michal
The following changes since commit
d7d000311285e4b8d11e089ca13ea456a01be3b8:
Merge branch 'master' of git://git.denx.de/u-boot-mips (2016-05-23
11:51:37 -0400)
are available in the git repository at:
git://www.denx.de/git/u-boot-microblaze.git master
for you to fetch changes up to ad5b5801264e573bfbf17a20b04c546985c5bfc1:
ARM: zynq: Simplify zynq configuration (2016-05-24 13:22:50 +0200)
----------------------------------------------------------------
Alexander Graf (1):
ARM64: zynqmp: Align gic ranges for 64k in device tree
Masahiro Yamada (2):
ARM: zynq: load u-boot.img whether CONFIG_OF_SEPARATE is defined
or not
ARM: dts: zynq: describe SLCR as simple-mfd rather than simple-bus
Michal Simek (27):
gpio: zynq: Add support for reading gpio pin state
ARM64: zynqmp: Enable HUSH parser for all zynqmp targets
ARM64: zynqmp: Enable missing distro default options
ARM64: zynqmp: Add support for reading MAC from eeprom
ARM64: zynqmp: Enable eMMC boot partitions commands
ARM64: zynqmp: Wire up debug_uart setup
ARM: zynq: Add support for SPL_LOAD_FIT
ARM64: zynqmp: Remove CONFIG_PREBOOT
ARM64: zynqmp: Enable SPI_FLASH and FLASH_BAR for ep108
ARM64: zynqmp: Add debug uart for zc1751-dc1
spl: Introduce new function spl_board_prepare_for_boot
ARM64: zynqmp: Enable option to overwrite default variables
ARM: zynq: Call ps7_post_config() for SPL
SPL: FIT: Enable SPL_FIT_LOAD in RAM based boot mode
tools: zynqmpimage: Add Xilinx ZynqMP boot header generation
ARM64: zynqmp: Add missing u-boot,dm-pre-reloc to DTSI
ARM64: zynqmp: Add SPL support support
ARM64: zynqmp: Enable CLK framework
fpga: Fix typo in function comment
mkimage: Report information about fpga
net: xilinx: Handle error value from phy_startup()
phy: Return correct error code when timeout happens
net: phy: Handle phy_startup() error codes properly
image: Add boot_get_fpga() to load fpga with bootm
phy: Wire return value from phy_config()
phy: marvell: Do not reset phy after negotiation
ARM: zynq: Simplify zynq configuration
arch/arm/Kconfig
| 1 +
arch/arm/cpu/armv8/zynqmp/Makefile
| 1 +
arch/arm/cpu/armv8/zynqmp/spl.c
| 107 +++++++++++++++++++++++++++++++++++++++++++++++++++++
arch/arm/dts/zynq-7000.dtsi
| 2 +-
arch/arm/dts/zynqmp.dtsi
| 9 ++++-
arch/arm/include/asm/arch-zynqmp/sys_proto.h
| 2 +
arch/arm/mach-zynq/Kconfig
| 48 +++---------------------
arch/arm/mach-zynq/spl.c
| 25 +++++++++++++
board/xilinx/zynq/Makefile
| 12 +-----
board/xilinx/zynq/custom_hw_platform/.gitignore
| 1 -
board/xilinx/zynq/{MicroZed_hw_platform =>
zynq-microzed}/ps7_init_gpl.c | 0
board/xilinx/zynq/{MicroZed_hw_platform =>
zynq-microzed}/ps7_init_gpl.h | 0
board/xilinx/zynq/{ZC702_hw_platform => zynq-zc702}/ps7_init_gpl.c
| 0
board/xilinx/zynq/{ZC702_hw_platform => zynq-zc702}/ps7_init_gpl.h
| 0
board/xilinx/zynq/{ZC706_hw_platform => zynq-zc706}/ps7_init_gpl.c
| 0
board/xilinx/zynq/{ZC706_hw_platform => zynq-zc706}/ps7_init_gpl.h
| 0
board/xilinx/zynq/{zed_hw_platform => zynq-zed}/ps7_init_gpl.c
| 0
board/xilinx/zynq/{zed_hw_platform => zynq-zed}/ps7_init_gpl.h
| 0
board/xilinx/zynq/{zybo_hw_platform => zynq-zybo}/ps7_init_gpl.c
| 0
board/xilinx/zynq/{zybo_hw_platform => zynq-zybo}/ps7_init_gpl.h
| 0
board/xilinx/zynqmp/Makefile
| 23 +++++++++++-
board/xilinx/zynqmp/xil_io.h
| 35 ++++++++++++++++++
board/xilinx/zynqmp/zynqmp.c
| 17 +++++++++
common/bootm.c
| 10 +++++
common/image-fit.c
| 11 +++++-
common/image.c
| 94 ++++++++++++++++++++++++++++++++++++++++++++++
common/spl/spl.c
| 51 ++++++++++++++++++++-----
configs/xilinx_zynqmp_ep_defconfig
| 9 +++++
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
| 8 ++++
configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
| 3 ++
configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
| 3 ++
configs/xilinx_zynqmp_zcu102_defconfig
| 8 ++++
configs/xilinx_zynqmp_zcu102_revB_defconfig
| 8 ++++
configs/zynq_microzed_defconfig
| 2 +-
configs/zynq_picozed_defconfig
| 2 +-
configs/zynq_zc702_defconfig
| 1 +
configs/zynq_zc706_defconfig
| 2 +-
configs/zynq_zc770_xm010_defconfig
| 2 +-
configs/zynq_zc770_xm011_defconfig
| 2 +-
configs/zynq_zc770_xm012_defconfig
| 2 +-
configs/zynq_zc770_xm013_defconfig
| 2 +-
configs/zynq_zed_defconfig
| 2 +-
configs/zynq_zybo_defconfig
| 2 +-
doc/uImage.FIT/multi-with-fpga.its
| 67 +++++++++++++++++++++++++++++++++
doc/uImage.FIT/source_file_format.txt
| 3 ++
drivers/fpga/fpga.c
| 2 +-
drivers/gpio/zynq_gpio.c
| 22 +++++++++++
drivers/net/phy/broadcom.c
| 34 +++++++++++------
drivers/net/phy/davicom.c
| 9 +++--
drivers/net/phy/et1011c.c
| 10 +++--
drivers/net/phy/lxt.c
| 9 +++--
drivers/net/phy/marvell.c
| 39 ++++++++++---------
drivers/net/phy/micrel.c
| 7 +++-
drivers/net/phy/natsemi.c
| 18 ++++++---
drivers/net/phy/phy.c
| 15 ++++----
drivers/net/phy/realtek.c
| 28 +++++++++-----
drivers/net/phy/smsc.c
| 10 +++--
drivers/net/phy/vitesse.c
| 8 ++--
drivers/net/xilinx_emaclite.c
| 6 ++-
drivers/net/zynq_gem.c
| 8 ++--
include/bootstage.h
| 1 +
include/configs/xilinx_zynqmp.h
| 59 ++++++++++++++++++++++++++++-
include/configs/xilinx_zynqmp_zcu102.h
| 6 +++
include/configs/zynq-common.h
| 6 +--
include/image.h
| 7 +++-
include/spl.h
| 1 +
scripts/Makefile.spl
| 7 ++++
tools/Makefile
| 1 +
tools/zynqmpimage.c
| 269
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
69 files changed, 1000 insertions(+), 159 deletions(-)
create mode 100644 arch/arm/cpu/armv8/zynqmp/spl.c
delete mode 100644 board/xilinx/zynq/custom_hw_platform/.gitignore
rename board/xilinx/zynq/{MicroZed_hw_platform =>
zynq-microzed}/ps7_init_gpl.c (100%)
rename board/xilinx/zynq/{MicroZed_hw_platform =>
zynq-microzed}/ps7_init_gpl.h (100%)
rename board/xilinx/zynq/{ZC702_hw_platform =>
zynq-zc702}/ps7_init_gpl.c (100%)
rename board/xilinx/zynq/{ZC702_hw_platform =>
zynq-zc702}/ps7_init_gpl.h (100%)
rename board/xilinx/zynq/{ZC706_hw_platform =>
zynq-zc706}/ps7_init_gpl.c (100%)
rename board/xilinx/zynq/{ZC706_hw_platform =>
zynq-zc706}/ps7_init_gpl.h (100%)
rename board/xilinx/zynq/{zed_hw_platform => zynq-zed}/ps7_init_gpl.c
(100%)
rename board/xilinx/zynq/{zed_hw_platform => zynq-zed}/ps7_init_gpl.h
(100%)
rename board/xilinx/zynq/{zybo_hw_platform =>
zynq-zybo}/ps7_init_gpl.c (100%)
rename board/xilinx/zynq/{zybo_hw_platform =>
zynq-zybo}/ps7_init_gpl.h (100%)
create mode 100644 board/xilinx/zynqmp/xil_io.h
create mode 100644 doc/uImage.FIT/multi-with-fpga.its
create mode 100644 tools/zynqmpimage.c
---
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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