[U-Boot] [PATCH 00/10] sunxi: Add basic PSCI support to enable SMP on the A80's first cluster

[Chen-Yu Tsai]

Hi,

On Wed, Nov 9, 2016 at 6:38 PM, Hans de Goede <hdegoede at redhat.com> wrote:
> Hi,
>
> On 09-11-16 11:21, Chen-Yu Tsai wrote:
>>
>> Hi everyone,
>>
>> This series adds basic PSCI support for the A80 to enable SMP on the
>> first cluster. This at least allows people to use more than one core.
>> The term "basic" is used because the series does not add support for
>> multi-cluster cache and power management.
>>
>> The PSCI code is based on existing code for all the single cluster
>> SoCs, and the kernel patches for MCPM SMP I did some time ago.
>>
>> Unfortunately only SMP works at this time. The last patch does not
>> actually work. While the system is indeed booted non-secure, tested
>> by trying to write to secure SRAM and the results not sticking, reads
>> from the GIC CPU interface shows that it's still returning the secure
>> copy of registers, and since we use a secure monitor FIQ to do core
>> power down, the FIQ gets passed to the kernel. The patch is included
>> so people with in-depth ARM knowledge could probably help work out
>> what is wrong.
>
>
> Cools stuff, when I find some time I will review and merge
> patches 1-9 to sunxi-next.
>
> First a question though, do you see any chance that merging this might
> get in the way of enabling support for both clusters in the future?
>
> Since the interface between u-boot and the kernel here is well defined
> (and outside our control) I guess in the worst case, we would need to
> revert some bits of this series from u-boot if they turn out to be non
> suitable, right?

So I started digging through why CPU power off is sending FIQs to the
kernel. So it turns out that the GIC base address programmed in the
CPU's CBAR is incorrect, so the GIC is not blocking secure interrupts,
and when the interrupt returns the CPU seems to get switched to secure
mode.

After hard-coding in the correct address, the system no longer boots.
It hangs when it tries to bring up the second core. I'm not sure
what's going on though. Need to add some more trace code.

I might have opened a can of worms...

ChenYu

>
> Regards,
>
> Hans
>
>
>
>
>>
>>
>> Regards
>> ChenYu
>>
>> Chen-Yu Tsai (10):
>>   ARM: PSCI: Set ARMV7_PSCI_NR_CPUS default to 8 for sun9i/A80
>>   sunxi: Add CCI-400 and CPUCFG registers base address for sun9i/A80
>>   sunxi: Add base address of secure SRAM B for sun9i/A80
>>   sunxi: Use secure SRAM B for secure RAM for sun9i/A80
>>   sunxi: Add PRCM register definition for sun9i/A80
>>   sunxi: Add CPUCFG register definitions for sun9i/A80
>>   sunxi: Add support for TZPC on sun9i/A80
>>   sunxi: Add basic PSCI implementation for A80
>>   sunxi: Enable PSCI on sun9i/A80
>>   sunxi: Add PSCI core power off support for A80's first cluster
>>
>>  arch/arm/cpu/armv7/Kconfig                     |   1 +
>>  arch/arm/cpu/armv7/sunxi/Makefile              |   5 +
>>  arch/arm/cpu/armv7/sunxi/psci-mcpm.c           | 322
>> +++++++++++++++++++++++++
>>  arch/arm/cpu/armv7/sunxi/tzpc.c                |   6 +
>>  arch/arm/include/asm/arch-sunxi/cpu_sun9i.h    |   5 +
>>  arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h |  51 ++++
>>  arch/arm/include/asm/arch-sunxi/prcm_sun9i.h   |  55 +++++
>>  arch/arm/include/asm/arch-sunxi/tzpc.h         |   4 +
>>  arch/arm/mach-sunxi/board.c                    |   3 +-
>>  board/sunxi/Kconfig                            |   4 +
>>  include/configs/sun9i.h                        |   4 +
>>  11 files changed, 459 insertions(+), 1 deletion(-)
>>  create mode 100644 arch/arm/cpu/armv7/sunxi/psci-mcpm.c
>>  create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h
>>  create mode 100644 arch/arm/include/asm/arch-sunxi/prcm_sun9i.h
>>
>