[U-Boot] [PATCHv3 04/15] arm: ls1021a: add PCIe dts node

[Zhiqiang Hou]

From: Minghuan Lian <Minghuan.Lian at nxp.com>

Signed-off-by: Minghuan Lian <Minghuan.Lian at nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
---
V3:
 - No change

 arch/arm/dts/ls1021a.dtsi | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 119b1af..e06cf60 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -373,5 +373,36 @@
 			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 			dr_mode = "host";
 		};
+
+		pcie at 3400000 {
+			compatible = "fsl,ls-pcie", "snps,dw-pcie";
+			reg = <0x03400000 0x20000   /* dbi registers */
+			       0x01570000 0x10000   /* pf controls registers */
+			       0x24000000 0x20000>; /* configuration space */
+			reg-names = "dbi", "ctrl", "config";
+			big-endian;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x24020000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x28000000 0x28000000 0x0 0x08000000>; /* non-prefetchable memory */
+		};
+
+		pcie at 3500000 {
+			compatible = "fsl,ls-pcie", "snps,dw-pcie";
+			reg = <0x03500000 0x10000    /* dbi registers */
+			       0x01570000 0x10000    /* pf controls registers */
+			       0x34000000 0x20000>;  /* configuration space */
+			reg-names = "dbi", "ctrl", "config";
+			big-endian;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			num-lanes = <2>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */
+		};
 	};
 };
-- 
2.1.0.27.g96db324