[U-Boot] [PATCH v2 2/3] ARM: DRA7: Redefine voltage and efuse macros per OPP using Kconfig

[Lokesh Vutla]

From: Suman Anna <s-anna at ti.com>

Redefine the macros used to define the voltage values and the
efuse register offsets based on OPP for all the voltage domains.
This is done using Kconfig macros that can be set in a defconfig
or selected during a config step. This allows a voltage domain
to be configured/set to a corresponding voltage value depending
on the OPP selection choice.

The Kconfig choices have been added for MPU, DSPEVE, IVA and GPU
voltage domains, with the MPU domain restricted to OPP_NOM. The
OPP_OD and OPP_HIGH options will be added when the support for
configuring the MPU clock frequency is added. The clock
configuration for other voltage domains is out of scope in
u-boot code.

The CORE voltage domain does not have separate voltage values
and efuse register offset at different OPPs, while the MPU
voltage domain only has different efuse register offsets for
different OPPs, but uses the same voltage value. Any different
choices of OPPs for voltage domains on common ganged-rails
is automatically taken care to select the corresponding
highest OPP voltage value.

Signed-off-by: Suman Anna <s-anna at ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla at ti.com>
---
 arch/arm/include/asm/arch-omap5/clock.h | 47 ++++++++++++-----
 arch/arm/mach-omap2/omap5/Kconfig       | 93 +++++++++++++++++++++++++++++++++
 2 files changed, 127 insertions(+), 13 deletions(-)

diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 551c927..e8b286b 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -286,19 +286,40 @@
 /* STD_FUSE_OPP_VMIN_MPU_4 */
 #define STD_FUSE_OPP_VMIN_MPU_HIGH	(DRA752_EFUSE_BASE + 0x1B28)
 
-/* Common voltage and Efuse register macros */
-/* DRA74x/DRA75x/DRA72x */
-#define VDD_MPU_DRA7			VDD_MPU_DRA7_NOM
-#define VDD_CORE_DRA7			VDD_CORE_DRA7_NOM
-#define VDD_EVE_DRA7			VDD_EVE_DRA7_NOM
-#define VDD_GPU_DRA7			VDD_GPU_DRA7_NOM
-#define VDD_IVA_DRA7			VDD_IVA_DRA7_NOM
-
-#define STD_FUSE_OPP_VMIN_MPU		STD_FUSE_OPP_VMIN_MPU_NOM
-#define STD_FUSE_OPP_VMIN_CORE		STD_FUSE_OPP_VMIN_CORE_NOM
-#define STD_FUSE_OPP_VMIN_DSPEVE	STD_FUSE_OPP_VMIN_DSPEVE_NOM
-#define STD_FUSE_OPP_VMIN_GPU		STD_FUSE_OPP_VMIN_GPU_NOM
-#define STD_FUSE_OPP_VMIN_IVA		STD_FUSE_OPP_VMIN_IVA_NOM
+#if defined(CONFIG_DRA7_MPU_OPP_HIGH)
+#define DRA7_MPU_OPP	OPP_HIGH
+#elif defined(CONFIG_DRA7_MPU_OPP_OD)
+#define DRA7_MPU_OPP	OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_MPU_OPP	OPP_NOM
+#endif
+
+/* OPP_NOM only available option for CORE */
+#define DRA7_CORE_OPP	OPP_NOM
+
+#if defined(CONFIG_DRA7_DSPEVE_OPP_HIGH)
+#define DRA7_DSPEVE_OPP	OPP_HIGH
+#elif defined(CONFIG_DRA7_DSPEVE_OPP_OD)
+#define DRA7_DSPEVE_OPP	OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_DSPEVE_OPP	OPP_NOM
+#endif
+
+#if defined(CONFIG_DRA7_IVA_OPP_HIGH)
+#define DRA7_IVA_OPP	OPP_HIGH
+#elif defined(CONFIG_DRA7_IVA_OPP_OD)
+#define DRA7_IVA_OPP	OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_IVA_OPP	OPP_NOM
+#endif
+
+#if defined(CONFIG_DRA7_GPU_OPP_HIGH)
+#define DRA7_GPU_OPP	OPP_HIGH
+#elif defined(CONFIG_DRA7_GPU_OPP_OD)
+#define DRA7_GPU_OPP	OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_GPU_OPP	OPP_NOM
+#endif
 
 /* Standard offset is 0.5v expressed in uv */
 #define PALMAS_SMPS_BASE_VOLT_UV 500000
diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig
index 22259dc..018e584 100644
--- a/arch/arm/mach-omap2/omap5/Kconfig
+++ b/arch/arm/mach-omap2/omap5/Kconfig
@@ -86,6 +86,99 @@ config TI_SECURE_EMIF_PROTECTED_REGION_SIZE
 	  using hardware memory firewalls. This value must be smaller than the
 	  TI_SECURE_EMIF_TOTAL_REGION_SIZE value.
 
+if TARGET_DRA7XX_EVM || TARGET_AM57XX_EVM
+menu "Voltage Domain OPP selections"
+
+choice
+	prompt "MPU Voltage Domain"
+	default DRA7_MPU_OPP_NOM
+        help
+	  Select the Operating Performance Point(OPP) for the MPU voltage
+	  domain on DRA7xx & AM57xx SoCs.
+
+config DRA7_MPU_OPP_NOM
+	bool "OPP NOM"
+	help
+	  This config option enables Normal OPP for MPU. This is the safest
+	  option for booting.
+
+endchoice
+
+choice
+	prompt "DSPEVE Voltage Domain"
+        help
+	  Select the Operating Performance Point(OPP) for the DSPEVE voltage
+	  domain on DRA7xx & AM57xx SoCs.
+
+config DRA7_DSPEVE_OPP_NOM
+	bool "OPP NOM"
+	help
+	  This config option enables Normal OPP for DSPEVE. This is the safest
+	  option for booting and choose this when unsure about other OPPs .
+
+config DRA7_DSPEVE_OPP_OD
+	bool "OPP OD"
+	help
+	  This config option enables Over drive OPP for DSPEVE.
+
+config DRA7_DSPEVE_OPP_HIGH
+	bool "OPP HIGH"
+	help
+	  This config option enables High OPP for DSPEVE.
+
+endchoice
+
+choice
+	prompt "IVA Voltage Domain"
+        help
+	  Select the Operating Performance Point(OPP) for the IVA voltage
+	  domain on DRA7xx & AM57xx SoCs.
+
+config DRA7_IVA_OPP_NOM
+	bool "OPP NOM"
+	help
+	  This config option enables Normal OPP for IVA. This is the safest
+	  option for booting and choose this when unsure about other OPPs .
+
+config DRA7_IVA_OPP_OD
+	bool "OPP OD"
+	help
+	  This config option enables Over drive OPP for IVA.
+
+config DRA7_IVA_OPP_HIGH
+	bool "OPP HIGH"
+	help
+	  This config option enables High OPP for IVA.
+
+endchoice
+
+choice
+	prompt "GPU Voltage Domain"
+        help
+	  Select the Operating Performance Point(OPP) for the GPU voltage
+	  domain on DRA7xx & AM57xx SoCs.
+
+config DRA7_GPU_OPP_NOM
+	bool "OPP NOM"
+	help
+	  This config option enables Normal OPP for GPU. This is the safest
+	  option for booting and choose this when unsure about other OPPs .
+
+config DRA7_GPU_OPP_OD
+	bool "OPP OD"
+	help
+	  This config option enables Over drive OPP for GPU.
+
+config DRA7_GPU_OPP_HIGH
+	bool "OPP HIGH"
+	help
+	  This config option enables High OPP for GPU.
+
+endchoice
+
+endmenu
+endif
+
 source "board/compulab/cm_t54/Kconfig"
 source "board/ti/omap5_uevm/Kconfig"
 source "board/ti/dra7xx/Kconfig"
-- 
2.10.1