[U-Boot] [PATCH 06/14] serial: 16550: Add Ingenic JZ4780 support

[Marek Vasut]

Add compatibility string for the Ingenic JZ4780 SoC, the necessary
UART enable bit into FCR and register shift. Neither are encoded
in the DTS coming from Linux, so we need to support it this way.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Tom Rini <trini at konsulko.com>
Cc: Simon Glass <sjg at chromium.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck at gmail.com>
Cc: Paul Burton <paul.burton at imgtec.com>
---
 drivers/serial/ns16550.c | 7 +++++++
 include/ns16550.h        | 3 +++
 2 files changed, 10 insertions(+)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 3130a1d..d00161c 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -363,6 +363,7 @@ int ns16550_serial_probe(struct udevice *dev)
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 enum {
 	PORT_NS16550 = 0,
+	PORT_JZ4780,
 };
 #endif
 
@@ -370,6 +371,7 @@ enum {
 int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
 {
 	struct ns16550_platdata *plat = dev->platdata;
+	const u32 port_type = dev_get_driver_data(dev);
 	fdt_addr_t addr;
 	struct clk clk;
 	int err;
@@ -439,6 +441,10 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
 	}
 
 	plat->fcr = UART_FCRVAL;
+	if (port_type == PORT_JZ4780) {
+		plat->fcr |= UART_FCR_UME;
+		plat->reg_shift = 2;
+	}
 
 	return 0;
 }
@@ -461,6 +467,7 @@ const struct dm_serial_ops ns16550_serial_ops = {
 static const struct udevice_id ns16550_serial_ids[] = {
 	{ .compatible = "ns16550",		.data = PORT_NS16550 },
 	{ .compatible = "ns16550a",		.data = PORT_NS16550 },
+	{ .compatible = "ingenic,jz4780-uart",	.data = PORT_JZ4780  },
 	{ .compatible = "nvidia,tegra20-uart",	.data = PORT_NS16550 },
 	{ .compatible = "snps,dw-apb-uart",	.data = PORT_NS16550 },
 	{ .compatible = "ti,omap2-uart",	.data = PORT_NS16550 },
diff --git a/include/ns16550.h b/include/ns16550.h
index 45fd68b..7c97036 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -118,6 +118,9 @@ typedef struct NS16550 *NS16550_t;
 #define UART_FCR_RXSR		0x02 /* Receiver soft reset */
 #define UART_FCR_TXSR		0x04 /* Transmitter soft reset */
 
+/* Ingenic JZ47xx specific UART-enable bit. */
+#define UART_FCR_UME		0x10
+
 /*
  * These are the definitions for the Modem Control Register
  */
-- 
2.10.2