[U-Boot] [RFC PATCH 3/3] spl: Add support for enabling dcache
Lokesh Vutla
lokeshvutla at ti.com
Mon Nov 28 10:34:45 CET 2016
Add support for enabling d-cache in SPL. The sequence in SPL tries to
replicate the sequence done in U-Boot except that MMU entries were added
for SRAM.
Signed-off-by: Lokesh Vutla <lokeshvutla at ti.com>
---
arch/arm/include/asm/cache.h | 1 +
arch/arm/lib/cache-cp15.c | 46 +++++++++++++++++++++++++++++++---------
arch/arm/mach-omap2/omap-cache.c | 15 +++++++++++++
common/spl/spl.c | 40 ++++++++++++++++++++++++++++++++++
4 files changed, 92 insertions(+), 10 deletions(-)
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index 5400cbe..20f6aca 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -39,6 +39,7 @@ void arm_init_before_mmu(void);
void arm_init_domains(void);
void cpu_cache_initialization(void);
void dram_bank_mmu_setup(int bank);
+void sram_bank_mmu_setup(phys_addr_t start, phys_addr_t size);
#endif
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index e9bbcf5..76f95d6 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -94,16 +94,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
mmu_page_table_flush(startpt, stoppt);
}
-__weak void dram_bank_mmu_setup(int bank)
+static void set_section_caches(int i)
{
- bd_t *bd = gd->bd;
- int i;
-
- debug("%s: bank: %d\n", __func__, bank);
- for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
- i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
- (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
- i++) {
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
set_section_dcache(i, DCACHE_WRITETHROUGH);
#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
@@ -111,9 +103,33 @@ __weak void dram_bank_mmu_setup(int bank)
#else
set_section_dcache(i, DCACHE_WRITEBACK);
#endif
- }
}
+__weak void dram_bank_mmu_setup(int bank)
+{
+ bd_t *bd = gd->bd;
+ int i;
+
+ debug("%s: bank: %d\n", __func__, bank);
+ for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
+ i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
+ (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT); i++)
+ set_section_caches(i);
+}
+
+#if defined(CONFIG_SPL_BUILD) && (defined(CONFIG_SPL_MAX_SIZE) || \
+ defined(CONFIG_SPL_MAX_FOOTPRINT))
+__weak void sram_bank_mmu_setup(phys_addr_t start, phys_addr_t size)
+{
+ int i;
+
+ for (i = start >> MMU_SECTION_SHIFT;
+ i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
+ i++)
+ set_section_caches(i);
+}
+#endif
+
/* to activate the MMU we need to set up virtual memory: use 1M areas */
static inline void mmu_setup(void)
{
@@ -129,6 +145,16 @@ static inline void mmu_setup(void)
dram_bank_mmu_setup(i);
}
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SPL_MAX_SIZE)
+ sram_bank_mmu_setup(CONFIG_SPL_TEXT_BASE,
+ ALIGN(CONFIG_SPL_MAX_SIZE, MMU_SECTION_SIZE));
+#elif defined(CONFIG_SPL_MAX_FOOTPRINT)
+ sram_bank_mmu_setup(CONFIG_SPL_TEXT_BASE,
+ ALIGN(CONFIG_SPL_MAX_FOOTPRINT, MMU_SECTION_SIZE));
+#endif
+#endif
+
#ifdef CONFIG_ARMV7_LPAE
/* Set up 4 PTE entries pointing to our 4 1GB page tables */
for (i = 0; i < 4; i++) {
diff --git a/arch/arm/mach-omap2/omap-cache.c b/arch/arm/mach-omap2/omap-cache.c
index b37163a..6019e0c 100644
--- a/arch/arm/mach-omap2/omap-cache.c
+++ b/arch/arm/mach-omap2/omap-cache.c
@@ -62,6 +62,21 @@ void dram_bank_mmu_setup(int bank)
set_section_dcache(i, ARMV7_DCACHE_POLICY);
}
+#ifdef CONFIG_SPL_BUILD
+void sram_bank_mmu_setup(phys_addr_t start, phys_addr_t size)
+{
+ int i;
+ phys_addr_t end;
+
+ start = start >> MMU_SECTION_SHIFT;
+ size = size >> MMU_SECTION_SHIFT;
+ end = start + size;
+
+ for (i = start; i <= end; i++)
+ set_section_dcache(i, ARMV7_DCACHE_POLICY);
+}
+#endif
+
void arm_init_domains(void)
{
u32 reg;
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 990b700..cdd2917 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -381,6 +381,34 @@ static int spl_load_image(struct spl_image_info *spl_image, u32 boot_device)
return -ENODEV;
}
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
+ defined(CONFIG_ARM)
+static int reserve_mmu(void)
+{
+ phys_addr_t ram_top = 0;
+ /* reserve TLB table */
+ gd->arch.tlb_size = PGTABLE_SIZE;
+
+#ifdef CONFIG_SYS_SDRAM_BASE
+ ram_top = CONFIG_SYS_SDRAM_BASE;
+#endif
+ ram_top += get_effective_memsize();
+ gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
+ debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
+ gd->arch.tlb_addr + gd->arch.tlb_size);
+ return 0;
+}
+
+__weak void dram_init_banksize(void)
+{
+#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = get_effective_memsize();
+#endif
+}
+
+#endif
+
void board_init_r(gd_t *dummy1, ulong dummy2)
{
u32 spl_boot_list[] = {
@@ -396,6 +424,13 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
debug(">>spl:board_init_r()\n");
gd->bd = &bdata;
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
+ defined(CONFIG_ARM)
+ dram_init_banksize();
+ reserve_mmu();
+ enable_caches();
+#endif
+
#if defined(CONFIG_SYS_SPL_MALLOC_START)
mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
CONFIG_SYS_SPL_MALLOC_SIZE);
@@ -432,6 +467,11 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
hang();
}
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
+ defined(CONFIG_ARM)
+ cleanup_before_linux();
+#endif
+
switch (spl_image.os) {
case IH_OS_U_BOOT:
debug("Jumping to U-Boot\n");
--
2.10.1
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