[U-Boot] [PATCH v2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

[Marek Vasut]

On 11/28/2016 10:37 AM, Vignesh R wrote:
> 
> 
> On Friday 25 November 2016 10:21 PM, Marek Vasut wrote:
>> On 11/24/2016 06:35 AM, Vignesh R wrote:
>>> According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC
>>> TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
>>> data interface writes until the last word of an indirect transfer
>>> otherwise indirect writes is known to fails sometimes. So, make sure
>>> that QSPI indirect writes are 32 bit sized except for the last write. If
>>> the txbuf is unaligned then use bounce buffer to avoid data aborts.
>>>
>>> So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER
>>> for all boards that use Cadence QSPI driver.
>>>
>>> [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
>>>
>>> Signed-off-by: Vignesh R <vigneshr at ti.com>
>>> ---
>>
>> Reviewed-by: Marek Vasut <marex at denx.de>
>>
>> I'd like to have at least Dinh's/Chin's ack on this.
>>
>> btw don't you need BB for READ as well ?
>>
> 
> I don't see any issue with READ due to non word size accesses ATM,

Like user does sf read ... 0x1003 0x100 , you'll likely have a problem, no?

> anyways I am working on patch to use BB for READ. Will post that separately.
> 
> Thanks for the review!
> 


-- 
Best regards,
Marek Vasut