[U-Boot] [PATCH v2 2/4] davinci: omapl138_lcdk: configure ddr2

[Fabien Parent]

On Tue, Nov 22, 2016 at 7:10 PM, Tom Rini <trini at konsulko.com> wrote:
> On Tue, Nov 22, 2016 at 06:13:31PM +0100, Fabien Parent wrote:
>
>> The SPL is unable to load u-boot because the DDR2 is not configured.
>> Configure the DDR2.
>>
>> Signed-off-by: Fabien Parent <fparent at baylibre.com>
>> ---
>>
>> V1 -> V2
>>
>>     * New patch
>>
>> ---
>>  include/configs/omapl138_lcdk.h | 42 +++++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 42 insertions(+)
>>
>> diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
>> index ce3a8f4..2cdf892 100644
>> --- a/include/configs/omapl138_lcdk.h
>> +++ b/include/configs/omapl138_lcdk.h
>> @@ -31,6 +31,7 @@
>>  #define CONFIG_SYS_HZ_CLOCK          clk_get(DAVINCI_AUXCLK_CLKID)
>>  #define CONFIG_SYS_HZ                        1000
>>  #define CONFIG_SYS_DA850_PLL_INIT
>> +#define CONFIG_SYS_DA850_DDR_INIT
>>  #define CONFIG_SKIP_LOWLEVEL_INIT
>>  #define CONFIG_SYS_TEXT_BASE         0xc1080000
>
> This would be "easy" to move to Kconfig, so please do.
>
>> @@ -80,6 +81,47 @@
>>  #define CONFIG_SYS_DA850_PLL1_PLLM     21
>>
>>  /*
>> + * DDR2 memory configuration
>> + */
>> +#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
>> +                                     DV_DDR_PHY_EXT_STRBEN | \
>> +                                     (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
>> +
>> +#define CONFIG_SYS_DA850_DDR2_SDBCR (                  \
>> +     (1 << DV_DDR_SDCR_DDR2EN_SHIFT)         | \
>> +     (1 << DV_DDR_SDCR_DDREN_SHIFT)          | \
>> +     (1 << DV_DDR_SDCR_SDRAMEN_SHIFT)        | \
>> +     (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)      | \
>> +     (4 << DV_DDR_SDCR_CL_SHIFT)             | \
>> +     (3 << DV_DDR_SDCR_IBANK_SHIFT)          | \
>> +     (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
>> +
>> +/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
>> +#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
>> +
>> +#define CONFIG_SYS_DA850_DDR2_SDTIMR (                 \
>> +     (19 << DV_DDR_SDTMR1_RFC_SHIFT)         | \
>> +     (1 << DV_DDR_SDTMR1_RP_SHIFT)           | \
>> +     (1 << DV_DDR_SDTMR1_RCD_SHIFT)          | \
>> +     (2 << DV_DDR_SDTMR1_WR_SHIFT)           | \
>> +     (6 << DV_DDR_SDTMR1_RAS_SHIFT)          | \
>> +     (8 << DV_DDR_SDTMR1_RC_SHIFT)           | \
>> +     (1 << DV_DDR_SDTMR1_RRD_SHIFT)          | \
>> +     (1 << DV_DDR_SDTMR1_WTR_SHIFT))
>> +
>> +#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (                \
>> +     (7 << DV_DDR_SDTMR2_RASMAX_SHIFT)       | \
>> +     (2 << DV_DDR_SDTMR2_XP_SHIFT)           | \
>> +     (0 << DV_DDR_SDTMR2_ODT_SHIFT)          | \
>> +     (10 << DV_DDR_SDTMR2_XSNR_SHIFT)        | \
>> +     (199 << DV_DDR_SDTMR2_XSRD_SHIFT)       | \
>> +     (1 << DV_DDR_SDTMR2_RTP_SHIFT)          | \
>> +     (2 << DV_DDR_SDTMR2_CKE_SHIFT))
>> +
>> +#define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000492
>> +#define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
>
> This is a little harder.  I think this should be done more like
> arch/arm/include/asm/arch-omap3/mem.h:#define where we name-space the
> values that we construct based on the part (maker and size/speed).  Do
> you have time to look into this migration?  Thanks!

Given that I don't have a lot of time right now, in the v3 I will just
move CONFIG_SYS_DA850_DDR_INIT to Kconfig and keep all the config in
the header file and at a later time once my current work on
OMAPl138-LCDK is over I will sent a new patchset for all the
CONFIG_SYS_DA85_DDR* options.

>
> --
> Tom