[U-Boot] [PATCH 7/9] armv8: ls2080a: add PCIe dts node

[Minghuan Lian]

Signed-off-by: Minghuan Lian <Minghuan.Lian at nxp.com>
---
 arch/arm/dts/fsl-ls2080a.dtsi | 60 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index b308c8b..4ed066f 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -75,4 +75,64 @@
 		reg-names = "QuadSPI", "QuadSPI-memory";
 		num-cs = <4>;
 	};
+
+	pcie at 3400000 {
+		compatible = "fsl,ls-pcie", "snps,dw-pcie";
+		reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
+		       0x00 0x03480000 0x0 0x80000   /* lut registers */
+		       0x10 0x00000000 0x0 0x20000>; /* configuration space */
+		reg-names = "dbi", "lut", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		num-lanes = <4>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+	};
+
+	pcie at 3500000 {
+		compatible = "fsl,ls-pcie", "snps,dw-pcie";
+		reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
+		       0x00 0x03580000 0x0 0x80000   /* lut registers */
+		       0x12 0x00000000 0x0 0x20000>; /* configuration space */
+		reg-names = "dbi", "lut", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		num-lanes = <4>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+	};
+
+	pcie at 3600000 {
+		compatible = "fsl,ls-pcie", "snps,dw-pcie";
+		reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
+		       0x00 0x03680000 0x0 0x80000   /* lut registers */
+		       0x14 0x00000000 0x0 0x20000>; /* configuration space */
+		reg-names = "dbi", "lut", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		num-lanes = <8>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+	};
+
+	pcie at 3700000 {
+		compatible = "fsl,ls-pcie", "snps,dw-pcie";
+		reg = <0x00 0x03700000 0x0 0x80000   /* dbi registers */
+		       0x00 0x03780000 0x0 0x80000   /* lut registers */
+		       0x16 0x00000000 0x0 0x20000>; /* configuration space */
+		reg-names = "dbi", "lut", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		num-lanes = <4>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+	};
 };
-- 
1.9.1