[U-Boot] [PATCH 5/9] armv8: ls1043a: add PCIe dts node

[Minghuan Lian]

Signed-off-by: Minghuan Lian <Minghuan.Lian at nxp.com>
---
 arch/arm/dts/fsl-ls1043a.dtsi | 46 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index a8bffba..a9894d0 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -215,5 +215,51 @@
 			big-endian;
 			status = "disabled";
 		};
+
+		pcie at 3400000 {
+			compatible = "fsl,ls-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03400000 0x0 0x10000   /* dbi registers */
+			       0x00 0x03410000 0x0 0x10000   /* lut registers */
+			       0x40 0x00000000 0x0 0x20000>; /* configuration space */
+			reg-names = "dbi", "lut", "config";
+			big-endian;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		};
+
+		pcie at 3500000 {
+			compatible = "fsl,ls-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03500000 0x0 0x10000   /* dbi registers */
+			       0x00 0x03510000 0x0 0x10000   /* lut registers */
+			       0x48 0x00000000 0x0 0x20000>; /* configuration space */
+			reg-names = "dbi", "lut", "config";
+			big-endian;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			num-lanes = <2>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		};
+
+		pcie at 3600000 {
+			compatible = "fsl,ls-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03600000 0x0 0x10000   /* dbi registers */
+			       0x00 0x03610000 0x0 0x10000   /* lut registers */
+			       0x50 0x00000000 0x0 0x20000>; /* configuration space */
+			reg-names = "dbi", "lut", "config";
+			big-endian;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		};
 	};
 };
-- 
1.9.1