[U-Boot] [PATCH 1/2] spi: ti_qspi: use 128 bit transfer mode when writing to flash

[Jagan Teki]

On Thu, Sep 1, 2016 at 1:24 PM, Vignesh R <vigneshr at ti.com> wrote:
> TI QSPI has four 32 bit data registers which can be used to transfer 16
> bytes of data at once. The register group QSPI_SPI_DATA_REG_3,
> QSPI_SPI_DATA_REG_2, QSPI_SPI_DATA_REG_1 and QSPI_SPI_DATA_REG is
> treated as a single 128-bit word for shifting data in and out. The bit
> at QSPI_SPI_DATA_REG_3[31] position is the first bit to be shifted out
> in case of 128 bit transfer mode. Therefore the first byte to be written
> to flash should be at QSPI_SPI_DATA_REG_3[31-25] position.
> Instead of writing 1 byte at a time when interacting with SPI NOR flash,
> make use of all the four registers so that 16 bytes can be transferred
> in one go.
>
> With this patch, the flash write speed increases from ~250KBs/ to
> ~650KB/s on DRA74 EVM.
>
> Signed-off-by: Vignesh R <vigneshr at ti.com>
> ---
>  drivers/spi/ti_qspi.c | 37 +++++++++++++++++++++++++++++++------
>  1 file changed, 31 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
> index bb72cb03ec24..fe2a280cc7ae 100644
> --- a/drivers/spi/ti_qspi.c
> +++ b/drivers/spi/ti_qspi.c
> @@ -23,6 +23,8 @@ DECLARE_GLOBAL_DATA_PTR;
>  #define QSPI_TIMEOUT                    2000000
>  #define QSPI_FCLK                      192000000
>  #define QSPI_DRA7XX_FCLK                76800000
> +#define QSPI_WLEN_MAX_BITS             128
> +#define QSPI_WLEN_MAX_BYTES            (QSPI_WLEN_MAX_BITS >> 3)
>  /* clock control */
>  #define QSPI_CLK_EN                     BIT(31)
>  #define QSPI_CLK_DIV_MAX                0xffff
> @@ -230,13 +232,33 @@ static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
>  #ifdef CONFIG_AM43XX
>         udelay(100);
>  #endif
> -       while (words--) {
> +       while (words) {
> +               u8 xfer_len = 0;
> +
>                 if (txp) {
> -                       debug("tx cmd %08x dc %08x data %02x\n",
> -                             priv->cmd | QSPI_WR_SNGL, priv->dc, *txp);
> -                       writel(*txp++, &priv->base->data);
> -                       writel(priv->cmd | QSPI_WR_SNGL,
> -                              &priv->base->cmd);
> +                       u32 cmd = priv->cmd;

Don't we require cmd mask for WLEN_MAX_BITS?

thanks!
-- 
Jagan.