[U-Boot] [PATCH 03/11] arm: socfpga: rstmgr: Segregate the Reset Manager for Stratix 10

[Marek Vasut]

On 08/22/2016 05:02 PM, Chin Liang See wrote:
> Segregate the Reset Manager to support both GEN5 SoC and
> Stratix 10 SoC.
> 
> Signed-off-by: Chin Liang See <clsee at altera.com>
> Cc: Marek Vasut <marex at denx.de>
> Cc: Dinh Nguyen <dinguyen at opensource.altera.com>
> Cc: Ley Foon Tan <lftan at altera.com>

Acked-by: Marek Vasut <marex at denx.de>

> ---
>  arch/arm/mach-socfpga/reset_manager.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
> index b6beaa2..0fa5f1a 100644
> --- a/arch/arm/mach-socfpga/reset_manager.c
> +++ b/arch/arm/mach-socfpga/reset_manager.c
> @@ -15,8 +15,10 @@ DECLARE_GLOBAL_DATA_PTR;
>  
>  static const struct socfpga_reset_manager *reset_manager_base =
>  		(void *)SOCFPGA_RSTMGR_ADDRESS;
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  static struct socfpga_system_manager *sysmgr_regs =
>  	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5) */
>  
>  /* Assert or de-assert SoCFPGA reset manager reset. */
>  void socfpga_per_reset(u32 reset, int set)
> @@ -31,8 +33,10 @@ void socfpga_per_reset(u32 reset, int set)
>  		reg = &reset_manager_base->per2_mod_reset;
>  	else if (RSTMGR_BANK(reset) == 3)
>  		reg = &reset_manager_base->brg_mod_reset;
> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
>  	else if (RSTMGR_BANK(reset) == 4)
>  		reg = &reset_manager_base->misc_mod_reset;
> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5) */
>  	else	/* Invalid reset register, do nothing */
>  		return;
>  
> @@ -60,9 +64,15 @@ void socfpga_per_reset_all(void)
>   */
>  void reset_cpu(ulong addr)
>  {
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  	/* request a warm reset */
>  	writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
>  		&reset_manager_base->ctrl);
> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> +	writel((1 << RSTMGR_MPUMODRST_CORE0),
> +		&reset_manager_base->mpu_mod_reset);
> +#endif
> +
>  	/*
>  	 * infinite loop here as watchdog will trigger and reset
>  	 * the processor
> @@ -92,6 +102,7 @@ void socfpga_bridges_reset(int enable)
>  
>  void socfpga_bridges_reset(int enable)
>  {
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  	const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
>  				L3REGS_REMAP_HPS2FPGA_MASK |
>  				L3REGS_REMAP_OCRAM_MASK;
> @@ -116,5 +127,6 @@ void socfpga_bridges_reset(int enable)
>  		/* Remap the bridges into memory map */
>  		writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
>  	}
> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5) */
>  }
>  #endif
> 


-- 
Best regards,
Marek Vasut