[U-Boot] [PATCH v2 11/11] arm: socfpga: Add support for Stratix 10 SoC dev kit
Chin Liang See
clsee at altera.com
Tue Sep 6 12:03:29 CEST 2016
Add support for Stratix 10 SoC development kit
Signed-off-by: Chin Liang See <clsee at altera.com>
Cc: Marek Vasut <marex at denx.de>
Cc: Dinh Nguyen <dinguyen at opensource.altera.com>
Cc: Ley Foon Tan <lftan at altera.com>
---
Changes for v2
- Sorting the config alphabetically
---
arch/arm/Kconfig | 7 +-
arch/arm/mach-socfpga/Kconfig | 10 +++
configs/socfpga_stratix10_defconfig | 14 ++++
include/configs/socfpga_stratix10_socdk.h | 135 ++++++++++++++++++++++++++++++
4 files changed, 163 insertions(+), 3 deletions(-)
create mode 100755 configs/socfpga_stratix10_defconfig
create mode 100644 include/configs/socfpga_stratix10_socdk.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index aef901c..c8e8767 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -600,10 +600,11 @@ config ARCH_SNAPDRAGON
config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
- select CPU_V7
- select SUPPORT_SPL
+ select CPU_V7 if !TARGET_SOCFPGA_STRATIX10
+ select ARM64 if TARGET_SOCFPGA_STRATIX10
+ select SUPPORT_SPL if !TARGET_SOCFPGA_STRATIX10
select OF_CONTROL
- select SPL_OF_CONTROL
+ select SPL_OF_CONTROL if !TARGET_SOCFPGA_STRATIX10
select DM
select DM_SPI_FLASH
select DM_SPI
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 1a43c7b..7a672ba 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -11,6 +11,9 @@ config TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_GEN5
bool
+config TARGET_SOCFPGA_STRATIX10
+ bool
+
choice
prompt "Altera SOCFPGA board select"
optional
@@ -43,6 +46,10 @@ config TARGET_SOCFPGA_SR1500
bool "SR1500 (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_STRATIX10_SOCDK
+ bool "Altera SOCFPGA SoCDK (Stratix 10)"
+ select TARGET_SOCFPGA_STRATIX10
+
config TARGET_SOCFPGA_TERASIC_DE0_NANO
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -62,11 +69,13 @@ config SYS_BOARD
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "sr1500" if TARGET_SOCFPGA_SR1500
+ default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+ default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
@@ -85,6 +94,7 @@ config SYS_CONFIG_NAME
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+ default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
endif
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
new file mode 100755
index 0000000..b17eb92
--- /dev/null
+++ b/configs/socfpga_stratix10_defconfig
@@ -0,0 +1,14 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_STRATIX10=y
+CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
+CONFIG_SYS_NS16550=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_CMD_MMC=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_USE_TINY_PRINTF=y
diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h
new file mode 100644
index 0000000..758c995
--- /dev/null
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __CONFIG_SOCFGPA_STRATIX10_H__
+#define __CONFIG_SOCFGPA_STRATIX10_H__
+
+#include <asm/arch/base_addr_s10.h>
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_TEXT_BASE 0x1000000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_LOADADDR 0x80000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_REMAKE_ELF
+# define COUNTER_FREQUENCY 0x01800000
+
+
+/*
+ * U-Boot console configurations
+ */
+#define CONFIG_IDENT_STRING "socfpga_stratix10"
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_FAT_WRITE
+#define CONFIG_DOS_PARTITION
+
+
+/*
+ * U-Boot run time memory configurations
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x40000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
+
+/*
+ * U-Boot display configurations
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * U-Boot environment configurations
+ */
+#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE 0x1000
+
+/*
+ * Boot arguments passed to the boot command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "rdinit=/sbin/init mem=2048M"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=n\0" \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "bootimage=Image\0" \
+ "fdt_addr=100\0" \
+ "fdtimage=socfpga_stratix10_swvp.dtb\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootimage};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+
+/*
+ * Generic Interrupt Controller Definitions
+ */
+#define CONFIG_GICV2
+#define GICD_BASE 0xFFFC1000
+#define GICC_BASE 0xFFFC2000
+
+/*
+ * External memory configurations
+ */
+#define PHYS_SDRAM_1 0x0
+#define PHYS_SDRAM_1_SIZE 0x40000000
+#define CONFIG_SYS_SDRAM_BASE 0
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_MEMTEST_START 0
+#define CONFIG_SYS_MEMTEST_END 0x100000
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
+#define CONFIG_SYS_NS16550_CLK 1000000
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Timer & watchdog configurations
+ */
+#define CONFIG_SYS_TIMERBASE SOCFPGA_SYSTIMER0_ADDRESS
+#define TIMER_LOAD_VAL 0xFFFFFFFF
+
+/*
+ * SDMMC configurations
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DWMMC
+#define CONFIG_SOCFPGA_DWMMC
+#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
+#endif
+/*
+ * Flash configurations
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_NO_FLASH
+
+
+#endif /* __CONFIG_H */
--
2.2.2
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