[U-Boot] [PATCH] arch: powerpc: update the eLBC IP input clock

[Prabhakar Kushwaha]

eLBC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock ratio register (LCRR) used in
current implementation governs eLBC IP output clock.

So update eLBC IP clock to be defined as per predefined clock
divisor of platform clock.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
---
 README                                    |  3 +++
 arch/powerpc/cpu/mpc85xx/speed.c          | 28 ++--------------------------
 arch/powerpc/include/asm/config.h         |  3 +++
 arch/powerpc/include/asm/config_mpc85xx.h |  5 +++++
 4 files changed, 13 insertions(+), 26 deletions(-)

diff --git a/README b/README
index 873a24c..ae89a3c 100644
--- a/README
+++ b/README
@@ -536,6 +536,9 @@ The following options need to be configured:
 		CONFIG_SYS_FSL_IFC_CLK_DIV
 		Defines divider of platform clock(clock input to IFC controller).
 
+		CONFIG_SYS_FSL_LBC_CLK_DIV
+		Defines divider of platform clock(clock input to eLBC controller).
+
 		CONFIG_SYS_FSL_PBL_PBI
 		It enables addition of RCW (Power on reset configuration) in built image.
 		Please refer doc/README.pblimage for more details
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index ea92ff3..0debda5 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -608,32 +608,8 @@ void get_sys_info(sys_info_t *sys_info)
 #endif /* CONFIG_FSL_CORENET */
 
 #if defined(CONFIG_FSL_LBC)
-	uint lcrr_div;
-#if defined(CONFIG_SYS_LBC_LCRR)
-	/* We will program LCRR to this value later */
-	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
-#else
-	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
-#endif
-	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
-#if defined(CONFIG_FSL_CORENET)
-		/* If this is corenet based SoC, bit-representation
-		 * for four times the clock divider values.
-		 */
-		lcrr_div *= 4;
-#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
-    !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
-		/*
-		 * Yes, the entire PQ38 family use the same
-		 * bit-representation for twice the clock divider values.
-		 */
-		lcrr_div *= 2;
-#endif
-		sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
-	} else {
-		/* In case anyone cares what the unknown value is */
-		sys_info->freq_localbus = lcrr_div;
-	}
+	sys_info->freq_localbus = sys_info->freq_systembus /
+						CONFIG_SYS_FSL_LBC_CLK_DIV;
 #endif
 
 #if defined(CONFIG_FSL_IFC)
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index bb23756..eb112df 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -84,6 +84,9 @@
 	defined(CONFIG_MPC83xx)
 #if !defined(CONFIG_FSL_IFC)
 #define CONFIG_FSL_LBC
+#ifndef CONFIG_SYS_FSL_LBC_CLK_DIV
+#define CONFIG_SYS_FSL_LBC_CLK_DIV	1
+#endif
 #endif
 #endif
 
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index fcfbb01..840951b 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -385,6 +385,7 @@
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
+#define CONFIG_SYS_FSL_LBC_CLK_DIV	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
@@ -423,6 +424,7 @@
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
+#define CONFIG_SYS_FSL_LBC_CLK_DIV	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
@@ -463,6 +465,7 @@
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_MAX_CPUS			8
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
+#define CONFIG_SYS_FSL_LBC_CLK_DIV	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		2
@@ -515,6 +518,7 @@
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
+#define CONFIG_SYS_FSL_LBC_CLK_DIV	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
@@ -551,6 +555,7 @@
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	3
+#define CONFIG_SYS_FSL_LBC_CLK_DIV	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		2
-- 
1.9.1