[U-Boot] [PATCH 04/11] arm: socfpga: clkmgr: Segregate the Clock Manager for Stratix 10

[Marek Vasut]

On 09/07/2016 03:26 PM, Chin Liang See wrote:
> On Tue, 2016-09-06 at 14:08 +0200, Marek Vasut wrote:
>> On 09/06/2016 07:14 AM, Chin Liang See wrote:
>>> On Mon, 2016-09-05 at 17:58 +0200, Marek Vasut wrote:
>>>> On 08/22/2016 05:02 PM, Chin Liang See wrote:
>>>>> Segregate the Clock Manager to support both GEN5 SoC and
>>>>> Stratix 10 SoC.
>>>>>
>>>>> Signed-off-by: Chin Liang See <clsee at altera.com>
>>>>> Cc: Marek Vasut <marex at denx.de>
>>>>> Cc: Dinh Nguyen <dinguyen at opensource.altera.com>
>>>>> Cc: Ley Foon Tan <lftan at altera.com>
>>>>> ---
>>>>>  arch/arm/mach-socfpga/clock_manager.c | 8 ++++++++
>>>>>  1 file changed, 8 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm/mach-socfpga/clock_manager.c
>>>>> b/arch/arm/mach
>>>>> -socfpga/clock_manager.c
>>>>> index aa71636..0d67b3c 100644
>>>>> --- a/arch/arm/mach-socfpga/clock_manager.c
>>>>> +++ b/arch/arm/mach-socfpga/clock_manager.c
>>>>> @@ -10,6 +10,7 @@
>>>>>  
>>>>>  DECLARE_GLOBAL_DATA_PTR;
>>>>>  
>>>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>>>  static const struct socfpga_clock_manager *clock_manager_base
>>>>> =
>>>>>  	(struct socfpga_clock_manager
>>>>> *)SOCFPGA_CLKMGR_ADDRESS;
>>>>>  
>>>>> @@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)
>>>>>  
>>>>>  	return clock;
>>>>>  }
>>>>> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>>>>>  
>>>>>  unsigned int cm_get_mmc_controller_clk_hz(void)
>>>>>  {
>>>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>>>  	uint32_t reg, clock = 0;
>>>>>  
>>>>>  	/* identify the source of MMC clock */
>>>>> @@ -475,8 +478,12 @@ unsigned int
>>>>> cm_get_mmc_controller_clk_hz(void)
>>>>>  	/* further divide by 4 as we have fixed divider at
>>>>> wrapper
>>>>> */
>>>>>  	clock /= 4;
>>>>>  	return clock;
>>>>> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
>>>>> +	return 25000000;
>>>>> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>>>>>  }
>>>>>  
>>>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>>>  unsigned int cm_get_qspi_controller_clk_hz(void)
>>>>
>>>> Are you sure this won't cause build breakage ? I believe this is
>>>> still
>>>> used by the cadence qspi driver.
>>>
>>> That is a good question. As for SOC Virtual Platform, we are not
>>> enabling the QSPI controller.
>>
>> When stratix 10 ships, this will be left broken then ?
>>
> 
> Definitely not as we will enable and validate this against emulation in
> coming weeks.

Great, thanks. U-Boot 2016.09 is out on sept. 12 , so that should give
you some space to clean this up.

-- 
Best regards,
Marek Vasut