[U-Boot] [PATCH 0/9] MIPS L2 cache support

[Paul Burton]

This series introduces support for initialising & maintaining L2 caches
on MIPS systems. This allows U-Boot to function correctly on systems
where such caches are present, whereas without performing L2 maintenance
it is likely to fail with cache coherence issues when writing code or
performing DMA transfers.

Paul Burton (9):
  MIPS: Add arch-wide arch_cpu_init
  MIPS: Probe cache line sizes once during boot
  MIPS: Enable use of the instruction cache earlier
  MIPS: Preserve Config implementation-defined bits
  MIPS: If we don't need DDR for cache init, init cache first
  MIPS: Define register names for cache init
  MIPS: Map CM Global Control Registers
  MIPS: L2 cache support
  MIPS: Malta: Enable CM & L2 support

 arch/mips/Kconfig                   |  28 +++++
 arch/mips/cpu/Makefile              |   2 +
 arch/mips/cpu/cm_init.S             |  45 +++++++
 arch/mips/cpu/cpu.c                 |   8 ++
 arch/mips/cpu/start.S               |  26 +++--
 arch/mips/include/asm/cache.h       |   9 ++
 arch/mips/include/asm/cm.h          |  57 +++++++++
 arch/mips/include/asm/global_data.h |   7 ++
 arch/mips/include/asm/mipsregs.h    |   6 +
 arch/mips/include/asm/u-boot-mips.h |  12 ++
 arch/mips/lib/cache.c               | 101 +++++++++++++---
 arch/mips/lib/cache_init.S          | 226 ++++++++++++++++++++++++++++++++----
 arch/mips/mach-ath79/cpu.c          |   3 +-
 board/imgtec/malta/lowlevel_init.S  |   6 -
 14 files changed, 482 insertions(+), 54 deletions(-)
 create mode 100644 arch/mips/cpu/cm_init.S
 create mode 100644 arch/mips/include/asm/cm.h

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2.9.3