[U-Boot] [PATCH 5/9] MIPS: If we don't need DDR for cache init, init cache first
Paul Burton
paul.burton at imgtec.com
Wed Sep 7 19:48:37 CEST 2016
On systems where cache initialisation doesn't require zeroed memory (ie.
systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined)
perform cache initialisation prior to lowlevel_init & DDR
initialisation. This allows for DDR initialisation code to run cached &
thus significantly faster.
Signed-off-by: Paul Burton <paul.burton at imgtec.com>
---
arch/mips/cpu/start.S | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index 6aec430..6f1d219 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -142,15 +142,24 @@ reset:
PTR_L gp, 0(ra)
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* Initialize any external memory */
PTR_LA t9, lowlevel_init
jalr t9
nop
+# endif
/* Initialize caches... */
PTR_LA t9, mips_cache_reset
jalr t9
nop
+
+# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
+ /* Initialize any external memory */
+ PTR_LA t9, lowlevel_init
+ jalr t9
+ nop
+# endif
#endif
/* Set up temporary stack */
--
2.9.3
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