[U-Boot] [PATCH v2] fsl-ifc-nand : Corrected the programming of chip select

[Prabhakar Kushwaha]

> -----Original Message-----
> From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Matt Weber
> Sent: Wednesday, September 07, 2016 9:12 PM
> To: u-boot at lists.denx.de
> Cc: scottwood at freescale.com; yorksun at freescale.com; Ronak Desai
> <ronak.desai at rockwellcollins.com>
> Subject: [U-Boot] [PATCH v2] fsl-ifc-nand : Corrected the programming of chip
> select
> 
> Corrected the chip selection in IFC_NAND_CSEL register. Due to this
> issue in multi-chip nand use-case, IFC was always pointing to the last
> probed chip even though the user select another device through "nand
> device <dev>" command.
> 
> Also, remove the usage of ifc_ctrl->cs_nand from driver as chipselect
> is a property of the chip not the controller.
> 
> Signed-off-by: Matthew Weber <matthew.weber at rockwellcollins.com>
> Signed-off-by: Ronak Desai <ronak.desai at rockwellcollins.com>
> 
> ---
> v1 -> v2
> [ Scott W
>  - Update fsl_ifc_sram_init() with correct csel and
>    cs_nand removed.
> ---
>  drivers/mtd/nand/fsl_ifc_nand.c | 12 +++++-------
>  1 file changed, 5 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
> index 7001cbd..1912fc1 100644
> --- a/drivers/mtd/nand/fsl_ifc_nand.c
> +++ b/drivers/mtd/nand/fsl_ifc_nand.c
> @@ -48,7 +48,6 @@ struct fsl_ifc_ctrl {
>  	/* device info */
>  	struct fsl_ifc regs;
>  	void __iomem *addr;      /* Address of assigned IFC buffer        */
> -	unsigned int cs_nand;    /* On which chipsel NAND is connected	  */
>  	unsigned int page;       /* Last page written to / read from      */
>  	unsigned int read_bytes; /* Number of bytes read during command   */
>  	unsigned int column;     /* Saved column from SEQIN               */
> @@ -296,7 +295,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
>  	int i;
> 
>  	/* set the chip select for NAND Transaction */
> -	ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
> +	ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank <<
> IFC_NAND_CSEL_SHIFT);
> 
>  	/* start read/write seq */
>  	ifc_out32(&ifc->ifc_nand.nandseq_strt,
> @@ -798,7 +797,7 @@ static void fsl_ifc_select_chip(struct mtd_info *mtd, int
> chip)
>  {
>  }
> 
> -static int fsl_ifc_sram_init(uint32_t ver)
> +static int fsl_ifc_sram_init(uint32_t ver, struct fsl_ifc_mtd *priv)
>  {
>  	struct fsl_ifc_runtime *ifc = ifc_ctrl->regs.rregs;
>  	uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
> @@ -823,7 +822,7 @@ static int fsl_ifc_sram_init(uint32_t ver)
>  		return 1;
>  	}
> 
> -	cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
> +	cs = priv->bank;
> 
>  	/* Save CSOR and CSOR_ext */
>  	csor = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor);
> @@ -850,7 +849,7 @@ static int fsl_ifc_sram_init(uint32_t ver)
>  	ifc_out32(&ifc->ifc_nand.col0, 0x0);
> 
>  	/* set the chip select for NAND Transaction */
> -	ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
> +	ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank <<
> IFC_NAND_CSEL_SHIFT);
> 
>  	/* start read seq */
>  	ifc_out32(&ifc->ifc_nand.nandseq_strt,
> IFC_NAND_SEQ_STRT_FIR_STRT);
> @@ -912,7 +911,6 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
> 
>  		if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) ==
> CSPR_MSEL_NAND &&
>  		    (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
> -			ifc_ctrl->cs_nand = priv->bank <<
> IFC_NAND_CSEL_SHIFT;
>  			break;
>  		}

{ } can be removed as "if" has only break statement. 

--prabhakar