[U-Boot] [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system initialization

[Z.Q. Hou]

Hi Prabhakar,

Thanks for your feedback!

> -----Original Message-----
> From: Prabhakar Kushwaha
> Sent: 2016年9月13日 18:04
> To: Z.Q. Hou <zhiqiang.hou at nxp.com>; u-boot at lists.denx.de;
> albert.u.boot at aribaud.net; york sun <york.sun at nxp.com>; Vincent Hu
> <mingkai.hu at nxp.com>; Calvin Johnson <calvin.johnson at nxp.com>
> Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system
> initialization
> 
> 
> > -----Original Message-----
> > From: Z.Q. Hou
> > Sent: Tuesday, September 13, 2016 2:39 PM
> > To: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>; u-
> > boot at lists.denx.de; albert.u.boot at aribaud.net; york sun
> > <york.sun at nxp.com>; Vincent Hu <mingkai.hu at nxp.com>; Calvin Johnson
> > <calvin.johnson at nxp.com>
> > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system
> > initialization
> >
> > Hi Prabhakar,
> >
> > Thanks for your feedback.
> >
> > > -----Original Message-----
> > > From: Prabhakar Kushwaha
> > > Sent: 2016年9月13日 15:22
> > > To: Z.Q. Hou <zhiqiang.hou at nxp.com>; u-boot at lists.denx.de;
> > > albert.u.boot at aribaud.net; york sun <york.sun at nxp.com>; Vincent Hu
> > > <mingkai.hu at nxp.com>; Calvin Johnson <calvin.johnson at nxp.com>
> > > Cc: Z.Q. Hou <zhiqiang.hou at nxp.com>
> > > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock
> > > system initialization
> > >
> > >
> > > > -----Original Message-----
> > > > From: Zhiqiang Hou [mailto:Zhiqiang.Hou at nxp.com]
> > > > Sent: Monday, September 12, 2016 9:39 AM
> > > > To: u-boot at lists.denx.de; albert.u.boot at aribaud.net; york sun
> > > > <york.sun at nxp.com>; Vincent Hu <mingkai.hu at nxp.com>; Prabhakar
> > > > Kushwaha <prabhakar.kushwaha at nxp.com>; Calvin Johnson
> > > > <calvin.johnson at nxp.com>
> > > > Cc: Z.Q. Hou <zhiqiang.hou at nxp.com>
> > > > Subject: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system
> > > > initialization
> > > >
> > > > From: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> > > >
> > > > This patch map the sys_info->freq_systembus to Platform PLL, and
> > > > implement the IPs' clock function individually.
> > > >
> > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
> > > > ---
> > > >  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 26
> > > > +++++++++++++++++--
> > > > ---
> > > >  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
> > > >  include/configs/ls2080a_common.h                   |  2 +-
> > > >  3 files changed, 22 insertions(+), 7 deletions(-)
> > > >
> > > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > > b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > > index a9b12a4..daad80a 100644
> > > > --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > > @@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info)
> > > > #endif  #endif
> > > >
> > > > +	/* The freq_systembus is used to record frequency of platform
> > > > +PLL */
> > > >  	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
> > > >  			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
> > > >  			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
> > > > -	/* Platform clock is half of platform PLL */
> > > > -	sys_info->freq_systembus /= 2;
> > >
> > > This is required only for ls2080A and ls2088A otherwise u-boot will
> > > be printing dicken speed in boot log.
> >
> > Why it is required by ls2080A and ls2088A? and I don't know what's
> > 'dicken speed'?
> >
> 
> Clock generated by SYSCLK * RCW[SYS_PLL_RAT] == dicken speed for LS2080
> and LS2088A.
> Platform clock or CCB = dicken speed/2

Why it is required by ls2080A and ls2088A but without #ifdef LS2080||LS2088?
Is there any document upon the concept 'dicken speed'? As you said the dicken speed == platform PLL frequency on LS2080A and LS2088A, what about other SoCs?
if the platform clock == dicken speed/2 on all Layerscape chassis2 and 3?

> 
> > >
> > > >  	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
> > > >  			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
> > > >  			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
> > > > @@ -132,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info)
> > > >  	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
> > > >  	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT)
> +
> > > > 1;
> > > >
> > > > -	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
> > > > +	sys_info->freq_localbus = sys_info->freq_systembus / 2 / ccr;
> > > >  #endif
> > > >  }
> > > >
> > > > @@ -159,7 +158,7 @@ int get_clocks(void)
> > > >
> > > >  /********************************************
> > > >   * get_bus_freq
> > > > - * return system bus freq in Hz
> > > > + * return platform PLL freq in Hz
> > > >   *********************************************/
> > > >  ulong get_bus_freq(ulong dummy)
> > > >  {
> > > > @@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num)
> > > >  	return gd->mem_clk;
> > > >  }
> > > >
> > > > +int get_i2c_freq(ulong dummy)
> > > > +{
> > > > +	return  get_bus_freq(0) / 4;
> > > > +}
> > > > +
> > > > +int get_dspi_freq(ulong dummy)
> > > > +{
> > > > +	return  get_bus_freq(0) / 4;
> > > > +}
> > > > +
> > > > +int get_serial_clock(void)
> > > > +{
> > > > +	return get_bus_freq(0) / 4;
> > > > +}
> > > > +
> > >
> > > get_bus_freq(0) / 4  --> May not be true for LS1088A. So Avoid this
> > > for above code.
> >
> > Will take LS1088A into account.
> >
> Thanks
> 

Thanks,
Zhiqiang