[U-Boot] [PATCH 8/9] arm: socfpga: de0-nano-soc: Adding handoff for SDRAM ctrlcfg.extratime1

[Chin Liang See]

Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stabil LPDDR2 operation

Signed-off-by: Chin Liang See <clsee at altera.com>
---
 board/terasic/de0-nano-soc/qts/sdram_config.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/terasic/de0-nano-soc/qts/sdram_config.h b/board/terasic/de0-nano-soc/qts/sdram_config.h
index 7084797..75aecda 100644
--- a/board/terasic/de0-nano-soc/qts/sdram_config.h
+++ b/board/terasic/de0-nano-soc/qts/sdram_config.h
@@ -33,6 +33,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
-- 
2.2.2