[U-Boot] [PATCH v3 13/14] MIPS: Clear hazard between TagLo writes & cache ops

[Paul Burton]

Writing to the coprocessor 0 TagLo registers introduces an execution
hazard in that we need that write to complete before any cache
instructions execute. Ensure that hazard is cleared by inserting an ehb
instruction between the TagLo writes & cache op loop.

Signed-off-by: Paul Burton <paul.burton at imgtec.com>

---

Changes in v3:
- New patch

Changes in v2: None

 arch/mips/lib/cache_init.S | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index e61432e..53e903a 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -293,6 +293,7 @@ l2_init:
 l1_init:
 	mtc0		zero, CP0_TAGLO
 	mtc0		zero, CP0_TAGLO, 2
+	ehb
 
 	/*
 	 * The caches are probably in an indeterminate state, so we force good
-- 
2.10.0