[U-Boot] [U-Boot, v4, 41/66] rockchip: clk: rk3368: implement DPLL (DRAM PLL) support

[Philipp Tomsich]

> To implement a TPL stage (incl. its DRAM controller setup) for the
> RK3368, we'll want to configure the DPLL (DRAM PLL).
> 
> This commit implements setting the DPLL (CLK_DDR) and provides PLL
> configuration details for the common DRAM operating speeds found on
> RK3368 boards.
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com>
> 
> Reviewed-by: Simon Glass <sjg at chromium.org>
> ---
> 
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> 
>  drivers/clk/rockchip/clk_rk3368.c | 35 +++++++++++++++++++++++++++++++++++
>  1 file changed, 35 insertions(+)
> 

Applied to u-boot-rockchip, thanks!