[U-Boot] rk3288: 32KB SPL size restriction

Jagan Teki jagannadh.teki at gmail.com
Wed Aug 23 11:19:34 UTC 2017

Hi Philipp,

On Tue, Aug 22, 2017 at 5:41 PM, Dr. Philipp Tomsich
<philipp.tomsich at theobroma-systems.com> wrote:
>> On 22 Aug 2017, at 14:05, Jagan Teki <jagannadh.teki at gmail.com> wrote:
>> Philipp and Kever - Thanks for the response.
>> Few comment below.
>> On Thu, Aug 17, 2017 at 2:02 PM, Dr. Philipp Tomsich
>> <philipp.tomsich at theobroma-systems.com> wrote:
>>> Jagan,
>>>> On 17 Aug 2017, at 08:39, Kever Yang <kever.yang at rock-chips.com> wrote:
>>>> Hi Jagan,
>>>> On 08/10/2017 05:07 PM, Jagan Teki wrote:
>>>>> Hi Simon/Philipp or any,
>>>>> I believe rk3288 has 20KB BootRom and 100KB internal SRAM and current
>>>>> u-boot can archive the maximum size of u-boot-spl-dtb.bin which the
>>>>> boot ROM will read is 32KB, do we have any possibility to increase the
>>>>> SPL size here.
>>>> The limitation is decide by the boot rom design, so we are not able
>>>> to change this. Most of Rockchip SoCs have this limitation except RK3399.
>>>> Thanks,
>>>> - Kever
>>>>> # ./tools/mkimage -n rk3288 -T rksd -d ./spl/u-boot-spl-dtb.bin out.img
>>>>> Warning: SPL image is too large (size 0x9000) and will not boot
>>>>> Error: image verification failed
>>>>> I tried to increase the spl_size from spl_infos (on tools/rkcommon.c)
>>>>> but not able to boot.
>>> I should have read this more carefully (I only parsed the 20KB and
>>> jumped to the conclusion that your had the error already when crossing
>>> the 20KB limit—even though 0x8000 bytes where allowed in mkimage)…
>> Sorry I really didn't understand the size constraint here, because SPL
>> can be boot file after ROM handoff. Can't this sit on 100KB of SRAM?
> The ROM usually has different size constraints for each stage.
> E.g. for the RK3368 (just been there, done that), the first stage has a
> 0x7000 byte limit and the next stage (loaded to 0x0 in DRAM) has a
> much larger limit. Note that the SRAM on the 3368 has a capacity of
> 0x10000 bytes, so the size limit is also quite pronounced.

OK, by looking at your rk3368[1] patch I think the first stage runs
under 0x7000 is TPL? and next stage(probably SPL) doesn't have limit
since SPL running here in DDR since DDR initialized DDR in TPL itself.
this is what the space distributed here?

[1] http://git.denx.de/?p=u-boot-rockchip.git;a=commitdiff;h=a55e4971569d2aa0150a1521876c928927e18471

Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

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