[U-Boot] rk3288: 32KB SPL size restriction

Dr. Philipp Tomsich philipp.tomsich at theobroma-systems.com
Tue Aug 22 12:11:44 UTC 2017


> On 22 Aug 2017, at 14:05, Jagan Teki <jagannadh.teki at gmail.com> wrote:
> 
> Philipp and Kever - Thanks for the response.
> 
> Few comment below.
> 
> On Thu, Aug 17, 2017 at 2:02 PM, Dr. Philipp Tomsich
> <philipp.tomsich at theobroma-systems.com> wrote:
>> Jagan,
>> 
>>> On 17 Aug 2017, at 08:39, Kever Yang <kever.yang at rock-chips.com> wrote:
>>> 
>>> Hi Jagan,
>>> 
>>> 
>>> On 08/10/2017 05:07 PM, Jagan Teki wrote:
>>>> Hi Simon/Philipp or any,
>>>> 
>>>> I believe rk3288 has 20KB BootRom and 100KB internal SRAM and current
>>>> u-boot can archive the maximum size of u-boot-spl-dtb.bin which the
>>>> boot ROM will read is 32KB, do we have any possibility to increase the
>>>> SPL size here.
>>> 
>>> The limitation is decide by the boot rom design, so we are not able
>>> to change this. Most of Rockchip SoCs have this limitation except RK3399.
>>> 
>>> Thanks,
>>> - Kever
>>>> 
>>>> # ./tools/mkimage -n rk3288 -T rksd -d ./spl/u-boot-spl-dtb.bin out.img
>>>> Warning: SPL image is too large (size 0x9000) and will not boot
>>>> Error: image verification failed
>>>> 
>>>> I tried to increase the spl_size from spl_infos (on tools/rkcommon.c)
>>>> but not able to boot.
>> 
>> I should have read this more carefully (I only parsed the 20KB and
>> jumped to the conclusion that your had the error already when crossing
>> the 20KB limit—even though 0x8000 bytes where allowed in mkimage)…
> 
> Sorry I really didn't understand the size constraint here, because SPL
> can be boot file after ROM handoff. Can't this sit on 100KB of SRAM?

The ROM usually has different size constraints for each stage.

E.g. for the RK3368 (just been there, done that), the first stage has a
0x7000 byte limit and the next stage (loaded to 0x0 in DRAM) has a
much larger limit. Note that the SRAM on the 3368 has a capacity of
0x10000 bytes, so the size limit is also quite pronounced.

My educate guess (I haven’t looked at the disassembly, though) is that
the BROM code needs some of the SRAM for scratch space while reading
the various memories.

Cheers,
Philipp.




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