[U-Boot] mv88e61xx autoneg doesn't work with new driver

[Clément Péron]

Hi,

I try to update my u-boot with the latest version 2017.07.

My board is an Altera SocFPGA CycloneV and I have a mv88e61xx switch.

My board is working fine except I got an issue with the new switch driver.
If autoneg is set to enable, negotation never complete and i got a timeout.
If I let the autoneg disable, I have ethernet working but with slow
speed 10mbits / half duplex.

Not sure if i'm doing something wrong or if there is a bug in the new driver.

Could you please help me to debug this issue ?

Thanks for your help,
Regards,
Clement

KConfig
####################################
--- Marvel MV88E61xx Ethernet switch PHY support.
(5)   CPU Port
(0x1F) Bitmask of PHY Ports
(0x0) Bitmask of PHYless serdes Ports


board.c
####################################
 int mv88e61xx_hw_reset(struct phy_device *phydev)
 {
         struct mii_dev *bus = phydev->bus;

         /* RGMII delay - Physical Control register bit[15:14] */
         debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
         /* forced 1000mbps full-duplex link */
         bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
         phydev->autoneg = AUTONEG_ENABLE;
         phydev->speed = SPEED_1000;
         phydev->duplex = DUPLEX_FULL;

         return 0;
 }

serial
####################################
U-Boot SPL 2017.07-00009-g9f00f9622e-dirty (Aug 31 2017 - 10:52:53)
drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
drivers/ddr/altera/sequencer.c: Calibration complete
Trying to boot from SPI


U-Boot 2017.07-00009-g9f00f9622e-dirty (Aug 31 2017 - 10:52:53 +0200)

CPU:   Altera SoCFPGA Platform
FPGA:  Altera Cyclone V, SE/A4 or SX/C4, version 0x0
BOOT:  QSPI Flash (3.0V)
       Watchdog enabled
DRAM:  512 MiB
MMC:   dwmmc0 at ff704000: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Model: Board
Net:   setting port5 RGMII rx/tx delay

Warning: ethernet at ff702000 (eth0) using random MAC address - 2e:91:a1:21:8e:38
eth0: ethernet at ff702000
Hit any key to stop autoboot:  0
=> tftp ${rootaddr} rootfs.cpio.uboot; tftp ${dtb_loadaddr} board.dtb;
tftp ${loadaddr} uImage; bootm ${loadaddr} ${rootaddr} ${dtb_loadadd}
ethernet at ff702000 Waiting for PHY auto negotiation to
complete......... TIMEOUT !
ethernet at ff702000 Waiting for PHY auto negotiation to
complete......... TIMEOUT !
ethernet at ff702000 Waiting for PHY auto negotiation to
complete......... TIMEOUT !
ethernet at ff702000 Waiting for PHY auto negotiation to
complete......... TIMEOUT !
ethernet at ff702000 Waiting for PHY auto negotiation to
complete......... TIMEOUT !
ethernet at ff702000: No link.
ethernet at ff702000 Waiting for PHY auto negotiation to
complete......... TIMEOUT !
ethernet at ff702000 Waiting for PHY auto negotiation to
complete......... TIMEOUT !
ethernet at ff702000 Waiting for PHY auto negotiation to
complete......... TIMEOUT !
ethernet at ff702000 Waiting for PHY auto negotiation to
complete......... TIMEOUT !
ethernet at ff702000 Waiting for PHY auto negotiation to
complete......... TIMEOUT !
ethernet at ff702000: No link.
ethernet at ff702000 Waiting for PHY auto negotiation to
complete......... TIMEOUT !
ethernet at ff702000 Waiting for PHY auto negotiation to
complete......... TIMEOUT !
ethernet at ff702000 Waiting for PHY auto negotiation to
complete......... TIMEOUT !
ethernet at ff702000 Waiting for PHY auto negotiation to
complete......... TIMEOUT !
ethernet at ff702000 Waiting for PHY auto negotiation to
complete......... TIMEOUT !
ethernet at ff702000: No link.
...