[U-Boot] [PATCH v2 2/2] board: ge: bx50v3: apply the proper register setting to fix the voltage peak issue

[Stefano Babic]

On 21/02/2017 02:56, Ken Lin wrote:
> Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register
> to avoid the voltage peak issue while we do the IEEE PHY comformance test
> 
> Signed-off-by: Ken Lin <yungching0725 at gmail.com>
> ---
> Changes from v1
> - New commit message
> 
>  board/ge/bx50v3/bx50v3.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
> index 80b4ba1b8b..0acf655c0e 100644
> --- a/board/ge/bx50v3/bx50v3.c
> +++ b/board/ge/bx50v3/bx50v3.c
> @@ -307,7 +307,8 @@ static int mx6_rgmii_rework(struct phy_device *phydev)
>  	/* set debug port address: SerDes Test and System Mode Control */
>  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
>  	/* enable rgmii tx clock delay */
> -	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
> +	/* set the reserved bits to avoid board specific voltage peak issue*/
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
>  
>  	return 0;
>  }
> 

Reviewed-by: Stefano Babic <sbabic at denx.de>

Best regards,
Stefano Babic

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