[U-Boot] [PATCH] armv8: fsl-lsch2: disable ECC for sata on armv8 chassis 2 platforms

[yuantian.tang at nxp.com]

From: Tang Yuantian <Yuantian.Tang at nxp.com>

The Read DMA operations get early termination indication from the
controller. This issue is observed as CRC error in the status
registers. The issue is due to address collision at address 0 in
the dual port memory. The read is a dummy read to flush out the
header, but due to collision the controller logs the mbit error
reported by the ECC check logic. This results in the early termination
of the Read DMA operation by the controller. The issue happens to
all the interface speeds(GEN1/2/3) for all the products.

In order to enable SATA, ECC needs to be disabled by writing  the data
0x80000000 to the address 0x20140520.

Signed-off-by: Tang Yuantian <yuantian.tang at nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 9489f85..b54a937 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -233,10 +233,8 @@ int sata_init(void)
 {
 	struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
 
-#ifdef CONFIG_ARCH_LS1046A
 	/* Disable SATA ECC */
 	out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
-#endif
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
 	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
-- 
2.1.0.27.g96db324