[U-Boot] [PATCH v2 07/10] powerpc, 8xx: Migrate to Kconfig
Bin Meng
bmeng.cn at gmail.com
Thu Jul 6 08:57:08 UTC 2017
Hi Christophe,
On Thu, Jul 6, 2017 at 4:33 PM, Christophe Leroy
<christophe.leroy at c-s.fr> wrote:
> Signed-off-by: Christophe Leroy <christophe.leroy at c-s.fr>
> ---
> README | 15 ----
> arch/powerpc/cpu/mpc8xx/Kconfig | 148 +++++++++++++++++++++++++++++++++++++
> arch/powerpc/cpu/mpc8xx/cpu_init.c | 2 +-
> arch/powerpc/cpu/mpc8xx/fec.c | 8 +-
> arch/powerpc/include/asm/ppc.h | 5 --
> drivers/i2c/soft_i2c.c | 2 +-
> scripts/config_whitelist.txt | 11 ---
> 7 files changed, 154 insertions(+), 37 deletions(-)
>
> diff --git a/README b/README
> index c3ab481a56..030a452f9a 100644
> --- a/README
> +++ b/README
> @@ -328,9 +328,6 @@ The following options need to be configured:
> multiple fs option at one time
> for marvell soc family
>
> -- 8xx CPU Options: (if using an MPC8xx CPU)
> - CONFIG_8xx_GCLK_FREQ - CPU clock
> -
> - 85xx CPU Options:
> CONFIG_SYS_PPC64
>
> @@ -3993,16 +3990,6 @@ Low Level (hardware related) configuration options:
> point to an otherwise UNUSED address space between
> the top of RAM and the start of the PCI space.
>
> -- CONFIG_SYS_SIUMCR: SIU Module Configuration (11-6)
> -
> -- CONFIG_SYS_SYPCR: System Protection Control (11-9)
> -
> -- CONFIG_SYS_TBSCR: Time Base Status and Control (11-26)
> -
> -- CONFIG_SYS_PISCR: Periodic Interrupt Status and Control (11-31)
> -
> -- CONFIG_SYS_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30)
> -
> - CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)
>
> - CONFIG_SYS_OR_TIMING_SDRAM:
> @@ -4011,8 +3998,6 @@ Low Level (hardware related) configuration options:
> - CONFIG_SYS_MAMR_PTA:
> periodic timer for refresh
>
> -- CONFIG_SYS_DER: Debug Event Register (37-47)
> -
> - FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
> CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
> CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
> diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
> index cb15dc5ebc..9e1ad33c28 100644
> --- a/arch/powerpc/cpu/mpc8xx/Kconfig
> +++ b/arch/powerpc/cpu/mpc8xx/Kconfig
> @@ -10,6 +10,21 @@ choice
>
> endchoice
>
> +choice
> + prompt "CPU select"
> + default MPC866
> +
> +config MPC866
> + bool "MPC866"
> +
> +config MPC885
> + bool "MPC885"
> +
> +endchoice
> +
> +config 8xx_GCLK_FREQ
> + int "CPU GCLK Frequency"
> +
> comment "Specific commands"
>
> config CMD_IMMAP
> @@ -19,4 +34,137 @@ config CMD_IMMAP
>
> siuinfo - print System Interface Unit (SIU) registers
> memcinfo - print Memory Controller registers
> +
> +comment "Configuration Registers"
> +
> +config SYS_SIUMCR
> + hex "SIUMCR register"
> + help
> + SIU Module Configuration (11-6)
> +
> +config SYS_SYPCR
> + hex "SYPCR register"
> + help
> + System Protection Control (11-9)
> +
> +config SYS_TBSCR
> + hex "TBSCR register"
> + help
> + Time Base Status and Control (11-26)
> +
> +config SYS_PISCR
> + hex "PISCR register"
> + help
> + Periodic Interrupt Status and Control (11-31)
> +
> +config SYS_PLPRCR_BOOL
> + bool "Customise PLPRCR"
> +
> +config SYS_PLPRCR
> + hex "PLPRCR register"
> + depends on SYS_PLPRCR_BOOL
> + help
> + PLL, Low-Power, and Reset Control Register (15-30)
> +
> +config SYS_SCCR
> + hex "SCCR register"
> + help
> + System Clock and reset Control Register (15-27)
> +
> +config SYS_SCCR_MASK
> + hex "MASK for setting SCCR register"
> +
> +config SYS_DER
> + hex "DER register"
> + help
> + Debug Event Register (37-47)
> +
> +comment "Memory mapping"
> +
> +config SYS_BR0_PRELIM
> + hex "Preliminary value for BR0"
> +
> +config SYS_OR0_PRELIM
> + hex "Preliminary value for OR0"
> +
These are really register values and should be converted to use device
tree, instead of Kconfig options.
> +config SYS_BR1_PRELIM_BOOL
> + bool "Define Bank 1"
> +
> +config SYS_BR1_PRELIM
> + hex "Preliminary value for BR1"
> + depends on SYS_BR1_PRELIM_BOOL
> +
> +config SYS_OR1_PRELIM
> + hex "Preliminary value for OR1"
> + depends on SYS_BR1_PRELIM_BOOL
> +
> +config SYS_BR2_PRELIM_BOOL
> + bool "Define Bank 2"
> +
> +config SYS_BR2_PRELIM
> + hex "Preliminary value for BR2"
> + depends on SYS_BR2_PRELIM_BOOL
> +
> +config SYS_OR2_PRELIM
> + hex "Preliminary value for OR2"
> + depends on SYS_BR2_PRELIM_BOOL
> +
> +config SYS_BR3_PRELIM_BOOL
> + bool "Define Bank 3"
> +
> +config SYS_BR3_PRELIM
> + hex "Preliminary value for BR3"
> + depends on SYS_BR3_PRELIM_BOOL
> +
> +config SYS_OR3_PRELIM
> + hex "Preliminary value for OR3"
> + depends on SYS_BR3_PRELIM_BOOL
> +
> +config SYS_BR4_PRELIM_BOOL
> + bool "Define Bank 4"
> +
> +config SYS_BR4_PRELIM
> + hex "Preliminary value for BR4"
> + depends on SYS_BR4_PRELIM_BOOL
> +
> +config SYS_OR4_PRELIM
> + hex "Preliminary value for OR4"
> + depends on SYS_BR4_PRELIM_BOOL
> +
> +config SYS_BR5_PRELIM_BOOL
> + bool "Define Bank 5"
> +
> +config SYS_BR5_PRELIM
> + hex "Preliminary value for BR5"
> + depends on SYS_BR5_PRELIM_BOOL
> +
> +config SYS_OR5_PRELIM
> + hex "Preliminary value for OR5"
> + depends on SYS_BR5_PRELIM_BOOL
> +
> +config SYS_BR6_PRELIM_BOOL
> + bool "Define Bank 6"
> +
> +config SYS_BR6_PRELIM
> + hex "Preliminary value for BR6"
> + depends on SYS_BR6_PRELIM_BOOL
> +
> +config SYS_OR6_PRELIM
> + hex "Preliminary value for OR6"
> + depends on SYS_BR6_PRELIM_BOOL
> +
> +config SYS_BR7_PRELIM_BOOL
> + bool "Define Bank 7"
> +
> +config SYS_BR7_PRELIM
> + hex "Preliminary value for BR7"
> + depends on SYS_BR7_PRELIM_BOOL
> +
> +config SYS_OR7_PRELIM
> + hex "Preliminary value for OR7"
> + depends on SYS_BR7_PRELIM_BOOL
> +
> +config SYS_IMMR
> + hex "Value for IMMR"
> +
> endmenu
[snip]
Regards,
Bin
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