[U-Boot] [PATCH v2] powerpc, 8xx: Add support for MCR3000 board from CSSI
Christophe LEROY
christophe.leroy at c-s.fr
Thu Jul 6 13:31:26 UTC 2017
Hello Heiko,
Le 06/07/2017 à 12:10, Heiko Schocher a écrit :
> Hello Christophe,
>
> Am 06.07.2017 um 10:39 schrieb Christophe Leroy:
>> CS Systemes d'Information (CSSI) manufactures two boards, named MCR3000
>> and CMPC885 which are respectively based on MPC866 and MPC885 processors.
>>
>> This patch adds support for the first board.
>>
>> Signed-off-by: Christophe Leroy <christophe.leroy at c-s.fr>
>> ---
>> Applies after the v2 serie 'powerpc, 8xx: Modernise the 8xx'
>>
>> .travis.yml | 2 +
>> arch/powerpc/cpu/mpc8xx/Kconfig | 5 +
>> board/cssi/MAINTAINERS | 6 +
>> board/cssi/MCR3000/Kconfig | 15 ++
>> board/cssi/MCR3000/MCR3000.c | 316
>> ++++++++++++++++++++++++++++++++++++++++
>> board/cssi/MCR3000/Makefile | 10 ++
>> board/cssi/MCR3000/nand.c | 65 +++++++++
>> board/cssi/MCR3000/u-boot.lds | 91 ++++++++++++
>> configs/MCR3000_defconfig | 81 ++++++++++
>> drivers/net/mpc8xx_fec.c | 20 +++
>> include/configs/MCR3000.h | 240 ++++++++++++++++++++++++++++++
>> 11 files changed, 851 insertions(+)
>> create mode 100644 board/cssi/MAINTAINERS
>> create mode 100644 board/cssi/MCR3000/Kconfig
>> create mode 100644 board/cssi/MCR3000/MCR3000.c
>> create mode 100644 board/cssi/MCR3000/Makefile
>> create mode 100644 board/cssi/MCR3000/nand.c
>> create mode 100644 board/cssi/MCR3000/u-boot.lds
>> create mode 100644 configs/MCR3000_defconfig
>> create mode 100644 include/configs/MCR3000.h
>
> Reviewed-by: Heiko Schocher <hs at denx.de>
>
> nitpicks only:
>
>> diff --git a/.travis.yml b/.travis.yml
>> index 6f14ec2396..226c8313b1 100644
>> --- a/.travis.yml
>> +++ b/.travis.yml
>> @@ -210,6 +210,8 @@ matrix:
>> - env:
>> - BUILDMAN="mpc86xx"
>> - env:
>> + - BUILDMAN="mpc8xx"
>> + - env:
>> - BUILDMAN="siemens"
>> - env:
>> - BUILDMAN="tegra"
>
> Can you give us a link, where you tried it on travis ?
https://travis-ci.org/chleroy/uboot/builds/250339570?utm_source=email&utm_medium=notification
>
> [...]
>> diff --git a/board/cssi/MCR3000/MCR3000.c b/board/cssi/MCR3000/MCR3000.c
>> new file mode 100644
>> index 0000000000..a84633a669
>> --- /dev/null
>> +++ b/board/cssi/MCR3000/MCR3000.c
>> @@ -0,0 +1,316 @@
>> +/*
>> + * Copyright (C) 2010-2017 CS Systemes d'Information
>> + * Florent Trinh Thai <florent.trinh-thai at c-s.fr>
>> + * Christophe Leroy <christophe.leroy at c-s.fr>
>> + *
>> + * Board specific routines for the MCR3000 board
>> + *
>> + * - initialisation
>> + * - memory controller
>> + * - serial io initialisation
>> + * - ethernet io initialisation
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <hwconfig.h>
>> +#include <mpc8xx.h>
>> +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
>> +#include <libfdt.h>
>> +#endif
>> +#include <asm/io.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +
>> +/*
>> -------------------------------------------------------------------------
>> + * constant
>> + */
>> +static const uint cs1_dram_table_66[] = {
>> + /* DRAM - single read. (offset 0 in upm RAM) */
>> + 0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
>> + 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
>> +
>> + /* DRAM - burst read. (offset 8 in upm RAM) */
>> + 0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00,
>> + 0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05,
>> + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
>> + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
>> +
>> + /* DRAM - single write. (offset 18 in upm RAM) */
>> + 0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804,
>> + 0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
>> +
>> + /* DRAM - burst write. (offset 20 in upm RAM) */
>> + 0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00,
>> + 0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404,
>> + 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
>> + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
>> +
>> + /* refresh (offset 30 in upm RAM) */
>> + 0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04,
>> + 0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF,
>> +
>> + /* init */
>> + 0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF,
>> +
>> + /* exception. (offset 3c in upm RAM) */
>> + 0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
>> +};
>> +
>> +/*
>> -------------------------------------------------------------------------
>> + * Device Tree Support
>> + */
>> +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
>> +static int fdt_set_node_and_value(void *blob, char *nodename, char
>> *regname,
>> + void *var, int size)
>> +{
>
> May we move this function to a common place, as I think others can
> reuse it also?
Ok, I add it in my TODO list.
My second board will use it too.
>
>> + int ret = 0;
>> + int nodeoffset = 0;
>> +
>> + nodeoffset = fdt_path_offset(blob, nodename);
>> + if (nodeoffset >= 0) {
>> + ret = fdt_setprop(blob, nodeoffset, regname, var, size);
>> + if (ret < 0)
>> + printf("ft_blob_update(): cannot set %s/%s property; err:
>> %s\n",
>
> wrong text "ft_blob_update()" the functions name is
> fdt_set_node_and_value().
Ok
>
>> + nodename, regname, fdt_strerror(ret));
>> + } else {
>> + printf("ft_blob_update(): cannot find %s node err:%s\n",
>> + nodename, fdt_strerror(nodeoffset));
>> + }
>> + return ret;
>> +}
>> +
>> +/*
>> + * update "brg" property in the blob
>> + */
>> +static void ft_blob_update(void *blob, bd_t *bd)
>> +{
>> + uchar enetaddr[6];
>> + __be32 brg_data = cpu_to_be32(bd->bi_busfreq);
>> +
>> + /* BRG */
>> + fdt_set_node_and_value(blob, "/soc/cpm", "brg-frequency", &brg_data,
>> + sizeof(brg_data));
>> +
>> + /* MAC addr */
>> + if (eth_getenv_enetaddr("ethaddr", enetaddr))
>> + fdt_set_node_and_value(blob, "ethernet0", "local-mac-address",
>> + enetaddr, sizeof(u8) * 6);
>> +
>> + /* Bus Frequency for CPM */
>> + fdt_set_node_and_value(blob, "/soc", "bus-frequency",
>> &bd->bi_busfreq,
>> + sizeof(u32));
>> +}
>
> Hmm... seems also a common functionality for me, or? May its better
> places in arch/powerpc/cpu/mpc8xx/fdt.c ft_cpu_setup()
Ok, I add it in my TODO list.
>
>> +
>> +static void ft_e1_setup(void *blob)
>> +{
>> + ulong data_rate = 2;
>> + ulong channel_phase = 0;
>> + char *sync = "receive";
>> +
>> + /* Set data rate */
>> + fdt_set_node_and_value(blob, "/localbus/e1-wan", "data-rate",
>> + &data_rate, sizeof(u32));
>> +
>> + /* Set channel phase to 0 */
>> + fdt_set_node_and_value(blob, "/localbus/e1-wan", "channel-phase",
>> + &channel_phase, sizeof(u32));
>> +
>> + /* rising edge sync pulse transmit */
>> + fdt_set_node_and_value(blob, "/localbus/e1-wan",
>> + "rising-edge-sync-pulse", sync,
>> + sizeof(u8) * strlen(sync));
>> +}
>> +
>> +void ft_board_setup(void *blob, bd_t *bd)
>> +{
>> + ft_cpu_setup(blob, bd);
>> + ft_blob_update(blob, bd);
>> + ft_e1_setup(blob);
>> +}
>> +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
>> +
>> +/*
>> -------------------------------------------------------------------------
>> + * Check Board Identity:
>> + */
>> +int checkboard(void)
>> +{
>> + serial_puts("BOARD: MCR3000 CSSI\n");
>> +
>> + return 0;
>> +}
>> +
>> +
>> +/*
>> -------------------------------------------------------------------------
>> + * Initialize SDRAM
>> + */
>> +int dram_init(void)
>> +{
>> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>> + memctl8xx_t __iomem *memctl = &immap->im_memctl;
>> +
>> + printf("UPMA init for SDRAM (CAS latency 2), ");
>> + printf("init address 0x%08x, size ", (int)dram_init);
>> + /* Configure UPMA for cs1 */
>> + upmconfig(UPMA, (uint *)cs1_dram_table_66,
>> + sizeof(cs1_dram_table_66) / sizeof(uint));
>> + udelay(10);
>> + out_be16(&memctl->memc_mptpr, 0x0200);
>> + out_be32(&memctl->memc_mamr, 0x14904000);
>> + udelay(10);
>> + out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
>> + out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
>> + udelay(10);
>> + out_be32(&memctl->memc_mcr, 0x80002830);
>> + out_be32(&memctl->memc_mar, 0x00000088);
>> + out_be32(&memctl->memc_mcr, 0x80002038);
>> + udelay(200);
>> +
>> + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
>> + SDRAM_MAX_SIZE);
>> +
>> + return 0;
>> +}
>> +
>> +/*
>> -------------------------------------------------------------------------
>> + * Miscelaneous init
>> + */
>> +
>> +#define ADDR_CPLD_R_ETAT ((unsigned short *)0x10000806)
>> +#define R_ID_CPLD_MASK 0xFF00
>> +
>> +#define ADDR_FLASH_ENV_AREA ((unsigned short *)0x04040000)
>> +
>> +struct environment {
>> + uint32_t crc;
>> + uint8_t data[];
>> +};
>> +
>> +
>> +#define LEN_STR 80
>> +
>> +int misc_init_r(void)
>> +{
>> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
>> + iop8xx_t __iomem *iop = &immr->im_ioport;
>> + char str[LEN_STR];
>> + char s_ethaddr[LEN_STR];
>> + char s_id_cpld[LEN_STR];
>> + char s_num_serie[LEN_STR];
>> + char s_password[LEN_STR];
>> + unsigned short version_cpld;
>> + struct environment *env;
>> + uint32_t crc;
>> + char *s;
>> + int i, j;
>> +
>> + /* --------------------------------------------
>> + * GPIO or per. Function
>> + * PCPAR[13] = 0 [0x0004] -> GPIO: (BTN_ACQ_AL)
>> + * -------------------------------------------- */
>> + clrsetbits_be16(&iop->iop_pcpar, 0, 0x4);
>> +
>> + /* ----------------------------------------------
>> + * In/Out or per. Function 0/1
>> + * PCDIR[13] = 1 [0x0004] -> GPIO: IN (CS_POT1_5V)
>> + * ---------------------------------------------- */
>> + clrsetbits_be16(&iop->iop_pcdir, 0, 0x4);
>> +
>> + /* if BTN_ACQ_IN is pressed then bootdelay is changed to 60
>> second */
>> + if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
>> + setenv("bootdelay", "60");
>> +
>> + /* verifying environment variable area */
>> + env = (struct environment *)CONFIG_ENV_ADDR;
>> + crc = crc32(0, env->data, (CONFIG_ENV_SIZE - sizeof(uint32_t)));
>
> What do you do here?
On this board, there is no EEPROM to store the Ethernet Address and
other vital information (serial number, password, CPLD version),
therefore when U-boot is upgraded (from Linux), the ETHERNET address is
writen in RAW text format in the environment area, so that at next
restart, U-boot includes it when it restores the default environment.
>
>> + if (crc != env->crc) {
>> + /* It can be an update request */
>> + for (i = 0; i < 8; i++) {
>> + str[i] = *(((uint8_t *)CONFIG_ENV_ADDR) + i);
>> + str[(i+1)] = 0;
>> + }
>> + if (strcmp(str, "ETHADDR=") == 0) {
>> + /* getting saved value */
>> + i = 0;
>> + for (j = 0; j < 4; j++) {
>> + while (*(((uint8_t *)CONFIG_ENV_ADDR) + i) !=
>> + '=')
>> + i++;
>> + switch (j) {
>> + case 0:
>> + s = s_ethaddr; break;
>
> checkpatch does not complain, but I think, we write the "break;" in the
> next line ...
Ok
>
>> + case 1:
>> + s = s_num_serie; break;
>> + case 2:
>> + s = s_id_cpld; break;
>> + case 3:
>> + s = s_password; break;
>> + }
>> + do {
>> + i++;
>> + *s = *(((uint8_t *)CONFIG_ENV_ADDR) + i);
>> + s++;
>> + } while (*(((uint8_t *)CONFIG_ENV_ADDR) + i)
>> + != 0x00);
>> + }
>> +
>> + /* creating or updating environment variable */
>> + if (s_ethaddr[0] != 0x00)
>> + setenv("ethaddr", s_ethaddr);
>> + if (s_num_serie[0] != 0x00)
>> + setenv("num_serie", s_num_serie);
>> + if (s_id_cpld[0] != 0x00)
>> + setenv("id_cpld", s_id_cpld);
>> + if (s_password[0] != 0x00)
>> + setenv("password", s_password);
>> + saveenv();
>> + }
>> + }
>> +
>> + /* we do not modify environment variable area if CRC is false */
>> + crc = crc32(0, env->data, (CONFIG_ENV_SIZE - sizeof(uint32_t)));
>> + if (crc == env->crc) {
>> + /* getting version value in CPLD register */
>> + for (i = 0; i < LEN_STR; i++)
>> + str[i] = 0;
>> + version_cpld = *ADDR_CPLD_R_ETAT & R_ID_CPLD_MASK;
>> + if (((version_cpld >> 12) & 0x000f) < 0x000a)
>> + str[0] = ((version_cpld >> 12) & 0x000f) + 0x30;
>> + else
>> + str[0] = (((version_cpld >> 12) & 0x000f) - 0x000a) +
>> + 0x41;
>> + if (((version_cpld >> 8) & 0x000f) < 0x000a)
>> + str[1] = ((version_cpld >> 8) & 0x000f) + 0x30;
>> + else
>> + str[1] = (((version_cpld >> 8) & 0x000f) - 0x000a) +
>> + 0x41;
>> + str[2] = 0x30;
>> + str[3] = 0x30;
>> +
>> + /* updating "id_cpld" variable if not corresponding */
>> + s = getenv("id_cpld");
>> + if ((s == NULL) || (strcmp(s, str) != 0)) {
>> + setenv("id_cpld", str);
>> + saveenv();
>> + }
>> + }
>
> Sorry, I do not understand, what you are doing here ...
There is a CPLD on the board. This piece of code reads the FW version in
the component and stores it in the environment in a variable named
'id_cpld'.
>
>> +
>> + return 0;
>> +}
>> +
>> +int board_early_init_f(void)
>> +{
>> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
>> +
>> + /*
>> + * Erase FPGA(s) for reboot
>> + */
>> + clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA
>> down */
>> + setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA
>> output */
>> + udelay(1); /* Wait more than 300ns */
>> + setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */
>> +
>> + return 0;
>> +}
>> diff --git a/board/cssi/MCR3000/Makefile b/board/cssi/MCR3000/Makefile
>> new file mode 100644
>> index 0000000000..401d5aa4c1
>> --- /dev/null
>> +++ b/board/cssi/MCR3000/Makefile
>> @@ -0,0 +1,10 @@
>> +#
>> +# Copyright (C) 2010-2017 CS Systemes d'Information
>> +# Christophe Leroy <christophe.leroy at c-s.fr>
>> +#
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +#
>> +
>> +obj-y += MCR3000.o
>> +obj-$(CONFIG_CMD_NAND) += nand.o
>> diff --git a/board/cssi/MCR3000/nand.c b/board/cssi/MCR3000/nand.c
>> new file mode 100644
>> index 0000000000..8e5b0d0618
>> --- /dev/null
>> +++ b/board/cssi/MCR3000/nand.c
>> @@ -0,0 +1,65 @@
>> +/*
>> + * Copyright (C) 2010-2017 CS Systemes d'Information
>> + * Florent Trinh Thai <florent.trinh-thai at c-s.fr>
>> + * Christophe Leroy <christophe.leroy at c-s.fr>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <config.h>
>> +#include <common.h>
>> +#include <nand.h>
>> +#include <asm/io.h>
>> +
>> +#define BIT_CLE ((unsigned short)0x0800)
>> +#define BIT_ALE ((unsigned short)0x0400)
>> +#define BIT_NCE ((unsigned short)0x1000)
>> +
>> +static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd,
>> unsigned int ctrl)
>> +{
>> + struct nand_chip *this = mtdinfo->priv;
>> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
>> + unsigned short pddat = 0;
>> +
>> + /* The hardware control change */
>> + if (ctrl & NAND_CTRL_CHANGE) {
>> + pddat = in_be16(&immr->im_ioport.iop_pddat);
>> +
>> + /* Clearing ALE and CLE */
>> + pddat &= ~(BIT_CLE | BIT_ALE);
>> +
>> + /* Driving NCE pin */
>> + if (ctrl & NAND_NCE)
>> + pddat &= ~BIT_NCE;
>> + else
>> + pddat |= BIT_NCE;
>> +
>> + /* Driving CLE and ALE pin */
>> + if (ctrl & NAND_CLE)
>> + pddat |= BIT_CLE;
>> + if (ctrl & NAND_ALE)
>> + pddat |= BIT_ALE;
>> +
>> + out_be16(&immr->im_ioport.iop_pddat, pddat);
>> + }
>> +
>> + /* Writing the command */
>> + if (cmd != NAND_CMD_NONE)
>> + out_8(this->IO_ADDR_W, cmd);
>> +}
>> +
>> +int board_nand_init(struct nand_chip *nand)
>> +{
>> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
>> +
>> + /* Set GPIO Port */
>> + setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00);
>> + clrbits_be16(&immr->im_ioport.iop_pdpar, 0x1c00);
>> + clrsetbits_be16(&immr->im_ioport.iop_pddat, 0x0c00, 0x1000);
>> +
>> + nand->chip_delay = 60;
>> + nand->ecc.mode = NAND_ECC_SOFT;
>> + nand->cmd_ctrl = nand_hwcontrol;
>> +
>> + return 0;
>> +}
>> diff --git a/board/cssi/MCR3000/u-boot.lds
>> b/board/cssi/MCR3000/u-boot.lds
>> new file mode 100644
>> index 0000000000..2234bd8d1d
>> --- /dev/null
>> +++ b/board/cssi/MCR3000/u-boot.lds
>
> I wonder why you need a board specific lds file?
Don't know, it was like this for other 8xx boards.
How should it be done indeed ?
>
>> @@ -0,0 +1,91 @@
>> +/*
>> + * Copyright (C) 2010-2017 CS Systemes d'Information
>> + * Christophe Leroy <christophe.leroy at c-s.fr>
>> + *
>> + * (C) Copyright 2001-2003
>> + * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
>> + *
>> + * Modified by Yuli Barcohen <yuli at arabellasw.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +OUTPUT_ARCH(powerpc)
>> +SECTIONS
>> +{
>> + /* Read-only sections, merged into text segment: */
>> + . = + SIZEOF_HEADERS;
>> + .text :
>> + {
>> + arch/powerpc/cpu/mpc8xx/start.o (.text)
>> + arch/powerpc/cpu/mpc8xx/start.o (.text*)
>> + arch/powerpc/cpu/mpc8xx/traps.o (.text*)
>> + arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
>> + arch/powerpc/lib/built-in.o (.text*)
>> + board/cssi/MCR3000/built-in.o (.text*)
>> + disk/built-in.o (.text*)
>> + drivers/net/built-in.o (.text*)
>> +
>> + *(.text)
>> + }
>> + _etext = .;
>> + PROVIDE (etext = .);
>> + .rodata :
>> + {
>> + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
>> + }
>> +
>> + /* Read-write section, merged into data segment: */
>> + . = (. + 0x0FFF) & 0xFFFFF000;
>> + _erotext = .;
>> + PROVIDE (erotext = .);
>> + .reloc :
>> + {
>> + _GOT2_TABLE_ = .;
>> + KEEP(*(.got2))
>> + KEEP(*(.got))
>> + _FIXUP_TABLE_ = .;
>> + KEEP(*(.fixup))
>> + }
>> + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
>> + __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
>> +
>> + .data :
>> + {
>> + *(.data*)
>> + *(.sdata*)
>> + }
>> + _edata = .;
>> + PROVIDE (edata = .);
>> +
>> + . = .;
>> +
>> + . = ALIGN(4);
>> + .u_boot_list : {
>> + KEEP(*(SORT(.u_boot_list*)));
>> + }
>> +
>> + . = .;
>> + __start___ex_table = .;
>> + __ex_table : { *(__ex_table) }
>> + __stop___ex_table = .;
>> +
>> + . = ALIGN(4096);
>> + __init_begin = .;
>> + .text.init : { *(.text.init) }
>> + .data.init : { *(.data.init) }
>> + . = ALIGN(4096);
>> + __init_end = .;
>> +
>> + __bss_start = .;
>> + .bss (NOLOAD) :
>> + {
>> + *(.bss*)
>> + *(.sbss*)
>> + *(COMMON)
>> + . = ALIGN(4);
>> + }
>> + __bss_end = . ;
>> + PROVIDE (end = .);
>> +}
>> +ENTRY(_start)
>> diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig
>> new file mode 100644
>> index 0000000000..f8120f4a0a
>> --- /dev/null
>> +++ b/configs/MCR3000_defconfig
>> @@ -0,0 +1,81 @@
>> +CONFIG_PPC=y
>> +CONFIG_8xx=y
>> +CONFIG_TARGET_MCR3000=y
>> +CONFIG_BOOTDELAY=5
>> +CONFIG_HUSH_PARSER=y
>> +# CONFIG_CMD_SETEXPR is not set
>> +CONFIG_CMD_NET=y
>> +CONFIG_CMD_DHCP=y
>> +# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set
>> +# CONFIG_MMC is not set
>> +CONFIG_MTD_NOR_FLASH=y
>> +# CONFIG_PCI is not set
>> +CONFIG_OF_LIBFDT=y
>> +CONFIG_SYS_PROMPT="S3K> "
>> +CONFIG_NETDEVICES=y
>> +CONFIG_MPC8XX_FEC=y
>> +
>> +CONFIG_CMD_SAVEENV=y
>> +CONFIG_CMD_FLASH=y
>> +CONFIG_CMD_MII=y
>> +CONFIG_CMD_PING=y
>> +CONFIG_CMD_ASKENV=y
>> +CONFIG_CMD_REGINFO=y
>> +CONFIG_CMD_MTDPARTS=y
>> +CONFIG_CMD_NAND=y
>> +# CONFIG_CMD_BDI is not set
>> +# CONFIG_CMD_ECHO is not set
>> +# CONFIG_CMD_FPGA is not set
>> +# CONFIG_CMD_IMI is not set
>> +# CONFIG_CMD_IMLS is not set
>> +# CONFIG_CMD_ITEST is not set
>> +# CONFIG_CMD_CONSOLE is not set
>> +# CONFIG_CMD_LOADB is not set
>> +# CONFIG_CMD_LOADS is not set
>> +# CONFIG_CMD_MD5SUM is not set
>> +# CONFIG_CMD_MISC is not set
>> +# CONFIG_CMD_SETGETDCR is not set
>> +# CONFIG_CMD_SHA1 is not set
>> +# CONFIG_CMD_SOURCE is not set
>> +CONFIG_CMD_IMMAP=y
>> +
>> +CONFIG_SYS_IMMR=0xFF000000
>> +
>> +CONFIG_SYS_OR0_PRELIM=0xFFC00926
>> +CONFIG_SYS_BR0_PRELIM=0x04000801
>> +CONFIG_SYS_BR1_PRELIM_BOOL=y
>> +CONFIG_SYS_BR1_PRELIM=0x00000081
>> +CONFIG_SYS_OR1_PRELIM=0xFE000E00
>> +CONFIG_SYS_BR2_PRELIM_BOOL=y
>> +CONFIG_SYS_BR2_PRELIM=0x08000801
>> +CONFIG_SYS_OR2_PRELIM=0xFFFF8F2A
>> +CONFIG_SYS_BR3_PRELIM_BOOL=y
>> +CONFIG_SYS_BR3_PRELIM=0x0C000401
>> +CONFIG_SYS_OR3_PRELIM=0xFFFF8142
>> +CONFIG_SYS_BR4_PRELIM_BOOL=y
>> +CONFIG_SYS_BR4_PRELIM=0x10000801
>> +CONFIG_SYS_OR4_PRELIM=0xFFFF8D08
>> +CONFIG_SYS_BR5_PRELIM_BOOL=y
>> +CONFIG_SYS_BR5_PRELIM=0x14000801
>> +CONFIG_SYS_OR5_PRELIM=0xFFFF8916
>> +CONFIG_SYS_BR6_PRELIM_BOOL=y
>> +CONFIG_SYS_BR6_PRELIM=0x18000801
>> +CONFIG_SYS_OR6_PRELIM=0xFFFF0908
>> +CONFIG_SYS_BR7_PRELIM_BOOL=y
>> +CONFIG_SYS_BR7_PRELIM=0x1C000001
>> +CONFIG_SYS_OR7_PRELIM=0xFFFF810A
>> +
>> +CONFIG_8xx_GCLK_FREQ=132000000
>> +
>> +CONFIG_SYS_SYPCR=0xFFFFFF8F
>> +CONFIG_SYS_SIUMCR=0x00600400
>> +CONFIG_SYS_TBSCR=0x00C3
>> +CONFIG_SYS_PISCR=0x0000
>> +CONFIG_SYS_PLPRCR_BOOL=y
>> +CONFIG_SYS_PLPRCR=0x00460004
>> +CONFIG_SYS_SCCR_MASK=0x60000000
>> +CONFIG_SYS_SCCR=0x00C20000
>> +CONFIG_SYS_DER=0x2002000F
>> +
>> +
>> +
>> diff --git a/drivers/net/mpc8xx_fec.c b/drivers/net/mpc8xx_fec.c
>> index b070d6696a..e525d3b593 100644
>> --- a/drivers/net/mpc8xx_fec.c
>> +++ b/drivers/net/mpc8xx_fec.c
>> @@ -413,6 +413,26 @@ static void fec_pin_init(int fecidx)
>> */
>> out_be16(&immr->im_ioport.iop_pdpar, 0x1fff);
>> out_be16(&immr->im_ioport.iop_pddir, 0x1fff);
>> +
>> +#if defined(CONFIG_TARGET_MCR3000)
>> + out_be16(&immr->im_ioport.iop_papar, 0xBBFF);
>> + out_be16(&immr->im_ioport.iop_padir, 0x04F0);
>> + out_be16(&immr->im_ioport.iop_paodr, 0x0000);
>> +
>> + out_be32(&immr->im_cpm.cp_pbpar, 0x000133FF);
>> + out_be32(&immr->im_cpm.cp_pbdir, 0x0003BF0F);
>> + out_be16(&immr->im_cpm.cp_pbodr, 0x0000);
>> +
>> + out_be16(&immr->im_ioport.iop_pcpar, 0x0400);
>> + out_be16(&immr->im_ioport.iop_pcdir, 0x0080);
>> + out_be16(&immr->im_ioport.iop_pcso , 0x0D53);
>> + out_be16(&immr->im_ioport.iop_pcint, 0x0000);
>> +
>> + out_be16(&immr->im_ioport.iop_pdpar, 0x03FE);
>> + out_be16(&immr->im_ioport.iop_pddir, 0x1C09);
>> +
>> + setbits_be32(&immr->im_ioport.utmode, 0x80);
>> +#endif
>> #endif
>>
>> #endif /* CONFIG_ETHER_ON_FEC1 */
>> diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h
>> new file mode 100644
>> index 0000000000..53d4e9468a
>> --- /dev/null
>> +++ b/include/configs/MCR3000.h
>> @@ -0,0 +1,240 @@
>> +/*
>> + * Copyright (C) 2010-2017 CS Systemes d'Information
>> + * Christophe Leroy <christophe.leroy at c-s.fr>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#ifndef __CONFIG_H
>> +#define __CONFIG_H
>> +
>> +/*-----------------------------------------------------------------------
>>
>> + * High Level Configuration Options
>> + * (easy to change)
>> + */
>> +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
>> +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
>> +
>> +#define CONFIG_EXTRA_ENV_SETTINGS \
>> + "sdram_type=SDRAM\0" \
>> + "flash_type=AM29LV160DB\0" \
>> + "loadaddr=0x400000\0" \
>> + "filename=uImage.lzma\0" \
>> + "nfsroot=/opt/ofs\0" \
>> + "dhcp_ip=ip=:::::eth0:dhcp\0" \
>> + "console_args=console=ttyCPM0,115200N8\0" \
>> + "flashboot=setenv bootargs " \
>> + "${console_args} " \
>> + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
>> + "mcr3k:eth0:off;" \
>> + "${ofl_args}; " \
>> + "bootm 0x04060000 - 0x04050000\0" \
>> + "tftpboot=setenv bootargs " \
>> + "${console_args} " \
>> + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
>> + "mcr3k:eth0:off " \
>> + "${ofl_args}; " \
>> + "tftp ${loadaddr} ${filename};" \
>> + "tftp 0xf00000 mcr3000.dtb;" \
>> + "bootm ${loadaddr} - 0xf00000\0" \
>> + "netboot=dhcp ${loadaddr} ${filename};" \
>> + "tftp 0xf00000 mcr3000.dtb;" \
>> + "setenv bootargs " \
>> + "root=/dev/nfs rw " \
>> + "${console_args} " \
>> + "${dhcp_ip};" \
>> + "bootm ${loadaddr} - 0xf00000\0" \
>> + "nfsboot=setenv bootargs " \
>> + "root=/dev/nfs rw nfsroot=${serverip}:${nfsroot} " \
>> + "${console_args} " \
>> + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
>> + "mcr3k:eth0:off;" \
>> + "bootm 0x04060000 - 0x04050000\0" \
>> + "dhcpboot=dhcp ${loadaddr} ${filename};" \
>> + "tftp 0xf00000 mcr3000.dtb;" \
>> + "setenv bootargs " \
>> + "${console_args} " \
>> + "${dhcp_ip} " \
>> + "${ofl_args}; " \
>> + "bootm ${loadaddr} - 0xf00000\0"
>> +
>> +#define CONFIG_BOOTDELAY 5
>> +
>> +#define CONFIG_IPADDR 192.168.0.3
>> +#define CONFIG_SERVERIP 192.168.0.1
>> +#define CONFIG_NETMASK 255.0.0.0
>
> You really use fix addresses?
By default in uboot, yes. That's the factory default.
>
>> +
>> +#define CONFIG_BOOTCOMMAND "run flashboot"
>> +#define CONFIG_BOOTARGS "ubi.mtd=4 root=ubi0:rootfs rw " \
>> + "rootfstype=ubifs rootflags=sync " \
>> + "console=ttyCPM0,115200N8 " \
>> + "ip=${ipaddr}:::${netmask}:mcr3k:eth0:off"
>> +
>> +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
>> +#undef CONFIG_LOADS_BAUD_CHANGE /* don't allow baudrate
>> change */
>> +
>> +#define CONFIG_WATCHDOG 1 /* watchdog enabled */
>> +
>> +
>> +
>> +/*-----------------------------------------------------------------------
>>
>> + * Password configuration.
>> + */
>> +#define CONFIG_AUTOBOOT_KEYED 1
>> +#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d
>> sec...\n"
>> +#define CONFIG_AUTOBOOT_DELAY_STR "root" /* 1st password */
>
> This are already in Kconfig, please move them to your defconfig file.
Ok
>
>> +
>> +
>> +
>> +/*-----------------------------------------------------------------------
>>
>> + * Miscellaneous configurable options
>> + */
>> +#define CONFIG_SYS_LONGHELP
>> +#define CONFIG_SYS_CBSIZE 256
>> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +
>> sizeof(CONFIG_SYS_PROMPT) + 16)
>> +#define CONFIG_SYS_MAXARGS 16
>> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
>> +
>> +#define CONFIG_CMDLINE_EDITING 1
>> +#ifdef CONFIG_HUSH_PARSER
>> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "S3K> "
>> +#endif
>> +
>> +#define CONFIG_SYS_MEMTEST_START 0x00002000
>> +#define CONFIG_SYS_MEMTEST_END 0x00800000
>> +
>> +#define CONFIG_SYS_LOAD_ADDR 0x200000
>> +
>> +#define CONFIG_SYS_HZ 1000
>> +
>> +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
>> +
>> +
>> +
>> +
>> +
>> +/*-----------------------------------------------------------------------
>>
>> + * Physical memory map of the MCR3000 board
>> + */
>> +
>> +#define ADDR_FLASH (CONFIG_SYS_BR0_PRELIM & 0xFFFF0000)
>> +#define ADDR_SDRAM (CONFIG_SYS_BR1_PRELIM & 0xFFFF0000)
>> +#define ADDR_RAMDP (CONFIG_SYS_BR2_PRELIM & 0xFFFF0000)
>> +#define ADDR_NAND (CONFIG_SYS_BR3_PRELIM & 0xFFFF0000)
>> +#define ADDR_MTSL1 ((CONFIG_SYS_BR4_PRELIM & 0xFFFF0000) |
>> 0x00000000)
>> +#define ADDR_MTSL2 ((CONFIG_SYS_BR4_PRELIM & 0xFFFF0000) |
>> 0x00000200)
>> +#define ADDR_E1 ((CONFIG_SYS_BR4_PRELIM & 0xFFFF0000) |
>> 0x00000400)
>> +#define ADDR_SEM ((CONFIG_SYS_BR4_PRELIM & 0xFFFF0000) | 0x00000600)
>> +#define ADDR_CPLD ((CONFIG_SYS_BR4_PRELIM & 0xFFFF0000) | 0x00000800)
>
> Where are this defines used?
Euh ... nowhere it seems.
ADDR_CPLD should be used in ADDR_CPLD_R_ETAT instead of hard coding it.
I'll fix it and remove the unneeded ones.
>
>> +
>> +/*-----------------------------------------------------------------------
>>
>> + * Definitions for initial stack pointer and data area (in DPRAM)
>> + */
>> +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
>> +#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00
>> +#define CONFIG_SYS_GBL_DATA_SIZE 64
>> +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
>> + CONFIG_SYS_GBL_DATA_SIZE)
>> +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
>> +
>> +
>> +
>> +/*-----------------------------------------------------------------------
>>
>> + * RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero)
>> + */
>> +#define CONFIG_SYS_SDRAM_BASE 0x00000000
>> +#define SDRAM_MAX_SIZE (32 * 1024 * 1024)
>> +
>> +
>> +
>> +/*-----------------------------------------------------------------------
>>
>> + * FLASH organization
>> + */
>> +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
>> +#define CONFIG_SYS_FLASH_CFI 1
>> +#define CONFIG_FLASH_CFI_DRIVER 1
>> +#define CONFIG_SYS_MAX_FLASH_BANKS 1
>> +#define CONFIG_SYS_MAX_FLASH_SECT 35
>> +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
>> +#define CONFIG_SYS_FLASH_WRITE_TOUT 500
>> +
>> +
>> +
>> +/*-----------------------------------------------------------------------
>>
>> + * For booting Linux, the board info and command line data
>> + * have to be in the first 8 MB of memory, since this is
>> + * the maximum mapped by the Linux kernel during initialization.
>> + */
>> +#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
>> +#define CONFIG_SYS_MONITOR_LEN (256 << 10)
>> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
>> +#define CONFIG_SYS_MALLOC_LEN (4096 << 10)
>> +
>> +
>> +
>> +/*-----------------------------------------------------------------------
>>
>> + * Environment Configuration
>> + */
>> +/* environment is in FLASH */
>> +#define CONFIG_ENV_IS_IN_FLASH 1
>> +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
>> +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
>> +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE +
>> CONFIG_SYS_MONITOR_LEN)
>> +#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
>> +#define CONFIG_ENV_OVERWRITE 1
>> +
>> +
>> +
>> +/*-----------------------------------------------------------------------
>>
>> + * Cache Configuration
>> + */
>> +#define CONFIG_SYS_CACHELINE_SIZE 16
>> +
>> +
>> +
>> +/*-----------------------------------------------------------------------
>>
>> + * Ethernet configuration part
>> + */
>> +#define CONFIG_SYS_DISCOVER_PHY 1
>> +#ifdef CONFIG_MPC8XX_FEC
>> +#define CONFIG_MII_INIT 1
>> +#endif
>> +
>> +
>> +
>> +/*-----------------------------------------------------------------------
>>
>> + * NAND configuration part
>> + */
>> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
>> +#define CONFIG_SYS_NAND_MAX_CHIPS 1
>> +#define CONFIG_SYS_NAND_BASE 0x0C000000
>> +
>> +
>> +
>> +/*-----------------------------------------------------------------------
>>
>> + * Pass open firmware flat tree
>> + */
>> +#define CONFIG_OF_LIBFDT 1
>> +#define CONFIG_OF_BOARD_SETUP 1
>
> Here too... already Kconfig symbols, please move to your board defconfig
Ok
>
>> +
>> +
>> +
>> +/*-----------------------------------------------------------------------
>>
>> + * Internal Definitions
>> + *
>> + * Boot Flags
>> + */
>> +#define BOOTFLAG_COLD 0x01
>> +#define BOOTFLAG_WARM 0x02
>> +
>> +
>> +
>> +/*-----------------------------------------------------------------------
>>
>> + * Misc Settings
>> + */
>> +#define CONFIG_LZMA
>> +#define CONFIG_SHA256
>
> Here too... already Kconfig symbols, please move to your board defconfig
Ok
>
>> +
>> +#define CONFIG_CMD_REGINFO
>
> Hmm... you enable this define also in your defconfig, but I cannot find
> it in a Kconfig file ...
>
> pollux:u-boot hs [mpc8xx_restore] $ grep -lr CMD_REGINFO . | grep Kconfig
> pollux:u-boot hs [mpc8xx_restore] $
>
> How did you got it in your "configs/MCR3000_defconfig" file?
Manually, my mistake.
>
> BTW: it would be nice to move this define to Kconfig ;-)
It also has impact on mpc85xx and mpc86xx.
My plan is to split cmd/reginfo.c into the three arches to get rid of
the #ifdefs (there is no common part indeed), and move to Kconfig. I put
it on my TODO list for August.
>
> bye,
> Heiko
Thanks for your review
Christophe
>> +
>> +#endif /* __CONFIG_H */
>>
>
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