[U-Boot] [PATCH 03/51] gdsys: Post ppc4xx removal cleanup

Mario Six mario.six at gdsys.cc
Fri Jul 14 12:54:49 UTC 2017


The ppc4xx architecture was recently removed, and with it several old
gdsys 44x boards, but some "debris" from these purged boards was left
over.

This patch removes these remnants (mostly entries in Makefiles, some now
superfluous data structures and some now obsolete config variables from
the whitelist).

Signed-off-by: Mario Six <mario.six at gdsys.cc>
---

 board/gdsys/common/Makefile   |   4 --
 board/gdsys/common/miiphybb.c | 128 ------------------------------------------
 include/gdsys_fpga.h          |  96 -------------------------------
 scripts/config_whitelist.txt  |  10 ----
 4 files changed, 238 deletions(-)
 delete mode 100644 board/gdsys/common/miiphybb.c

diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index d4f0e70573..6f2fea207f 100644
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -7,10 +7,6 @@
 
 obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
 obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o
-obj-$(CONFIG_IO) += miiphybb.o
-obj-$(CONFIG_IO64) += miiphybb.o
-obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o ch7301.o
-obj-$(CONFIG_DLVISION_10G) += osd.o dp501.o
 obj-$(CONFIG_CONTROLCENTERD) += dp501.o
 obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o
 obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
diff --git a/board/gdsys/common/miiphybb.c b/board/gdsys/common/miiphybb.c
deleted file mode 100644
index 310562902b..0000000000
--- a/board/gdsys/common/miiphybb.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * (C) Copyright 2010
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach at gdsys.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-
-#include <asm/io.h>
-
-struct io_bb_pinset {
-	int mdio;
-	int mdc;
-};
-
-static int io_bb_mii_init(struct bb_miiphy_bus *bus)
-{
-	return 0;
-}
-
-static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
-{
-	struct io_bb_pinset *pins = bus->priv;
-
-	out_be32((void *)GPIO0_TCR,
-		in_be32((void *)GPIO0_TCR) | pins->mdio);
-
-	return 0;
-}
-
-static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
-{
-	struct io_bb_pinset *pins = bus->priv;
-
-	out_be32((void *)GPIO0_TCR,
-		in_be32((void *)GPIO0_TCR) & ~pins->mdio);
-
-	return 0;
-}
-
-static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
-{
-	struct io_bb_pinset *pins = bus->priv;
-
-	if (v)
-		out_be32((void *)GPIO0_OR,
-			in_be32((void *)GPIO0_OR) | pins->mdio);
-	else
-		out_be32((void *)GPIO0_OR,
-			in_be32((void *)GPIO0_OR) & ~pins->mdio);
-
-	return 0;
-}
-
-static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
-{
-	struct io_bb_pinset *pins = bus->priv;
-
-	*v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0);
-
-	return 0;
-}
-
-static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
-{
-	struct io_bb_pinset *pins = bus->priv;
-
-	if (v)
-		out_be32((void *)GPIO0_OR,
-			in_be32((void *)GPIO0_OR) | pins->mdc);
-	else
-		out_be32((void *)GPIO0_OR,
-			in_be32((void *)GPIO0_OR) & ~pins->mdc);
-
-	return 0;
-}
-
-static int io_bb_delay(struct bb_miiphy_bus *bus)
-{
-	udelay(1);
-
-	return 0;
-}
-
-struct io_bb_pinset io_bb_pinsets[] = {
-	{
-		.mdio = CONFIG_SYS_MDIO_PIN,
-		.mdc = CONFIG_SYS_MDC_PIN,
-	},
-#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
-	{
-		.mdio = CONFIG_SYS_MDIO1_PIN,
-		.mdc = CONFIG_SYS_MDC1_PIN,
-	},
-#endif
-};
-
-struct bb_miiphy_bus bb_miiphy_buses[] = {
-	{
-		.name = CONFIG_SYS_GBIT_MII_BUSNAME,
-		.init = io_bb_mii_init,
-		.mdio_active = io_bb_mdio_active,
-		.mdio_tristate = io_bb_mdio_tristate,
-		.set_mdio = io_bb_set_mdio,
-		.get_mdio = io_bb_get_mdio,
-		.set_mdc = io_bb_set_mdc,
-		.delay = io_bb_delay,
-		.priv = &io_bb_pinsets[0],
-	},
-#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
-	{
-		.name = CONFIG_SYS_GBIT_MII1_BUSNAME,
-		.init = io_bb_mii_init,
-		.mdio_active = io_bb_mdio_active,
-		.mdio_tristate = io_bb_mdio_tristate,
-		.set_mdio = io_bb_set_mdio,
-		.get_mdio = io_bb_get_mdio,
-		.set_mdc = io_bb_set_mdc,
-		.delay = io_bb_delay,
-		.priv = &io_bb_pinsets[1],
-	},
-#endif
-};
-
-int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
-			  sizeof(bb_miiphy_buses[0]);
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index bb8e144e04..34d6eeb253 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -87,81 +87,6 @@ struct ihs_fpga {
 };
 #endif
 
-#ifdef CONFIG_IO
-struct ihs_fpga {
-	u16 reflection_low;	/* 0x0000 */
-	u16 versions;		/* 0x0002 */
-	u16 fpga_features;	/* 0x0004 */
-	u16 fpga_version;	/* 0x0006 */
-	u16 reserved_0[5];	/* 0x0008 */
-	u16 quad_serdes_reset;	/* 0x0012 */
-	u16 reserved_1[8181];	/* 0x0014 */
-	u16 reflection_high;	/* 0x3ffe */
-};
-#endif
-
-#ifdef CONFIG_IO64
-struct ihs_fpga_channel {
-	u16 status_int;
-	u16 config_int;
-	u16 switch_connect_config;
-	u16 tx_destination;
-};
-
-struct ihs_fpga_hicb {
-	u16 status_int;
-	u16 config_int;
-};
-
-struct ihs_fpga {
-	u16 reflection_low;	/* 0x0000 */
-	u16 versions;		/* 0x0002 */
-	u16 fpga_features;	/* 0x0004 */
-	u16 fpga_version;	/* 0x0006 */
-	u16 reserved_0[5];	/* 0x0008 */
-	u16 quad_serdes_reset;	/* 0x0012 */
-	u16 reserved_1[502];	/* 0x0014 */
-	struct ihs_fpga_channel ch[32];		/* 0x0400 */
-	struct ihs_fpga_channel hicb_ch[32];	/* 0x0500 */
-	u16 reserved_2[7487];	/* 0x0580 */
-	u16 reflection_high;	/* 0x3ffe */
-};
-#endif
-
-#ifdef CONFIG_IOCON
-struct ihs_fpga {
-	u16 reflection_low;	/* 0x0000 */
-	u16 versions;		/* 0x0002 */
-	u16 fpga_version;	/* 0x0004 */
-	u16 fpga_features;	/* 0x0006 */
-	u16 reserved_0[1];	/* 0x0008 */
-	u16 top_interrupt;	/* 0x000a */
-	u16 reserved_1[4];	/* 0x000c */
-	struct ihs_gpio gpio;	/* 0x0014 */
-	u16 mpc3w_control;	/* 0x001a */
-	u16 reserved_2[2];	/* 0x001c */
-	struct ihs_io_ep ep;	/* 0x0020 */
-	u16 reserved_3[9];	/* 0x002e */
-	struct ihs_i2c i2c0;	/* 0x0040 */
-	u16 reserved_4[10];	/* 0x004c */
-	u16 mc_int;		/* 0x0060 */
-	u16 mc_int_en;		/* 0x0062 */
-	u16 mc_status;		/* 0x0064 */
-	u16 mc_control;		/* 0x0066 */
-	u16 mc_tx_data;		/* 0x0068 */
-	u16 mc_tx_address;	/* 0x006a */
-	u16 mc_tx_cmd;		/* 0x006c */
-	u16 mc_res;		/* 0x006e */
-	u16 mc_rx_cmd_status;	/* 0x0070 */
-	u16 mc_rx_data;		/* 0x0072 */
-	u16 reserved_5[69];	/* 0x0074 */
-	u16 reflection_high;	/* 0x00fe */
-	struct ihs_osd osd0;	/* 0x0100 */
-	u16 reserved_6[889];	/* 0x010e */
-	u16 videomem0[2048];	/* 0x0800 */
-};
-#endif
-
 #if defined(CONFIG_HRCON) || defined(CONFIG_STRIDER_CON_DP)
 struct ihs_fpga {
 	u16 reflection_low;	/* 0x0000 */
@@ -271,25 +196,4 @@ struct ihs_fpga {
 };
 #endif
 
-#ifdef CONFIG_DLVISION_10G
-struct ihs_fpga {
-	u16 reflection_low;	/* 0x0000 */
-	u16 versions;		/* 0x0002 */
-	u16 fpga_version;	/* 0x0004 */
-	u16 fpga_features;	/* 0x0006 */
-	u16 reserved_0[10];	/* 0x0008 */
-	u16 extended_interrupt; /* 0x001c */
-	u16 reserved_1[29];	/* 0x001e */
-	u16 mpc3w_control;	/* 0x0058 */
-	u16 reserved_2[3];	/* 0x005a */
-	struct ihs_i2c i2c0;	/* 0x0060 */
-	u16 reserved_3[2];	/* 0x006c */
-	struct ihs_i2c i2c1;	/* 0x0070 */
-	u16 reserved_4[194];	/* 0x007c */
-	struct ihs_osd osd0;	/* 0x0200 */
-	u16 reserved_5[761];	/* 0x020e */
-	u16 videomem0[2048];	/* 0x0800 */
-};
-#endif
-
 #endif
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index e261d02455..4c136a6502 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -499,7 +499,6 @@ CONFIG_DISCONTIGMEM
 CONFIG_DISCOVER_PHY
 CONFIG_DISPLAY_AER_xxxx
 CONFIG_DISPLAY_BOARDINFO_LATE
-CONFIG_DLVISION_10G
 CONFIG_DM9000_BASE
 CONFIG_DM9000_BYTE_SWAPPED
 CONFIG_DM9000_DEBUG
@@ -1167,9 +1166,6 @@ CONFIG_INI_MAX_SECTION
 CONFIG_INTEGRITY
 CONFIG_INTEL_ICH6_GPIO
 CONFIG_INTERRUPTS
-CONFIG_IO
-CONFIG_IO64
-CONFIG_IOCON
 CONFIG_IODELAY_RECALIBRATION
 CONFIG_IOMUX_LPSR
 CONFIG_IOMUX_SHARE_CONF_REG
@@ -3410,8 +3406,6 @@ CONFIG_SYS_GAFR2_L_VAL
 CONFIG_SYS_GAFR2_U_VAL
 CONFIG_SYS_GAFR3_L_VAL
 CONFIG_SYS_GAFR3_U_VAL
-CONFIG_SYS_GBIT_MII1_BUSNAME
-CONFIG_SYS_GBIT_MII_BUSNAME
 CONFIG_SYS_GBL_DATA_OFFSET
 CONFIG_SYS_GBL_DATA_SIZE
 CONFIG_SYS_GENERIC_BOARD
@@ -3857,13 +3851,9 @@ CONFIG_SYS_MCKR_VAL
 CONFIG_SYS_MCLINK_MAX
 CONFIG_SYS_MCMEM0_VAL
 CONFIG_SYS_MCMEM1_VAL
-CONFIG_SYS_MDC1_PIN
 CONFIG_SYS_MDCNFG_VAL
-CONFIG_SYS_MDC_PIN
 CONFIG_SYS_MDIO1_OFFSET
-CONFIG_SYS_MDIO1_PIN
 CONFIG_SYS_MDIO_BASE_ADDR
-CONFIG_SYS_MDIO_PIN
 CONFIG_SYS_MDMRS_VAL
 CONFIG_SYS_MDREFR_VAL
 CONFIG_SYS_MECR_VAL
-- 
2.11.0



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