[U-Boot] [PATCH 16/51] gpio: mpc85xx_gpio: Make compatible with MPC8XXX
Mario Six
mario.six at gdsys.cc
Fri Jul 14 12:55:02 UTC 2017
Since the GPIO controllers on MPC8XXX just vary in the number of pins
offered, the DM driver for the MPC85XX SoC can be used for the whole
family.
To reflect this, we rename the mpc85xx_gpio driver to the more generic
mpc8xxx_gpio, and add the needed mpc8xxx_gpio_plat structure to the
mpc83xx gpio.h.
Hence, this driver now also serves as a GPIO DM-driver for the MPC83XX
platform.
Signed-off-by: Mario Six <mario.six at gdsys.cc>
---
arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 8 +
arch/powerpc/include/asm/arch-mpc85xx/gpio.h | 2 +-
drivers/gpio/Kconfig | 9 +-
drivers/gpio/Makefile | 2 +-
drivers/gpio/mpc85xx_gpio.c | 253 -------------------------
drivers/gpio/mpc8xxx_gpio.c | 274 +++++++++++++++++++++++++++
6 files changed, 287 insertions(+), 261 deletions(-)
delete mode 100644 drivers/gpio/mpc85xx_gpio.c
create mode 100644 drivers/gpio/mpc8xxx_gpio.c
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
index 40ef2151b8..6ec4f00022 100644
--- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
@@ -19,7 +19,15 @@
#define MAX_NUM_GPIOS (32 * MPC83XX_GPIO_CTRLRS)
+struct mpc8xxx_gpio_plat {
+ ulong addr;
+ unsigned long size;
+ uint ngpios;
+};
+
+#ifndef DM_GPIO
void mpc83xx_gpio_init_f(void);
void mpc83xx_gpio_init_r(void);
+#endif /* DM_GPIO */
#endif /* MPC83XX_GPIO_H_ */
diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
index 76faa22c8b..b2ba31e623 100644
--- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
@@ -18,7 +18,7 @@
#include <asm/mpc85xx_gpio.h>
#endif
-struct mpc85xx_gpio_plat {
+struct mpc8xxx_gpio_plat {
ulong addr;
unsigned long size;
uint ngpios;
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 15135e538d..4e37e2179e 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -239,11 +239,11 @@ config DM_PCA953X
Now, max 24 bits chips and PCA953X compatible chips are
supported
-config MPC85XX_GPIO
- bool "Freescale MPC85XX GPIO driver"
+config MPC8XXX_GPIO
+ bool "Freescale MPC8XXX GPIO driver"
depends on DM_GPIO
help
- This driver supports the built-in GPIO controller of MPC85XX CPUs.
+ This driver supports the built-in GPIO controller of MPC8XXX CPUs.
Each GPIO bank is identified by its own entry in the device tree,
i.e.
@@ -261,7 +261,4 @@ config MPC85XX_GPIO
Aside from the standard functions of input/output mode, and output
value setting, the open-drain feature, which can configure individual
GPIOs to work as open-drain outputs, is supported.
-
- The driver has been tested on MPC85XX, but it is likely that other
- PowerQUICC III devices will work as well.
endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 8937e99b47..3f38555ab0 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -37,7 +37,7 @@ obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
obj-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o
obj-$(CONFIG_ALTERA_PIO) += altera_pio.o
obj-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
-obj-$(CONFIG_MPC85XX_GPIO) += mpc85xx_gpio.o
+obj-$(CONFIG_MPC8XXX_GPIO) += mpc8xxx_gpio.o
obj-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o
obj-$(CONFIG_OMAP_GPIO) += omap_gpio.o
obj-$(CONFIG_DB8500_GPIO) += db8500_gpio.o
diff --git a/drivers/gpio/mpc85xx_gpio.c b/drivers/gpio/mpc85xx_gpio.c
deleted file mode 100644
index 4566c091b7..0000000000
--- a/drivers/gpio/mpc85xx_gpio.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- * (C) Copyright 2016
- * Mario Six, Guntermann & Drunck GmbH, six at gdsys.de
- *
- * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
- *
- * Copyright 2010 eXMeritus, A Boeing Company
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/gpio.h>
-#include <mapmem.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct ccsr_gpio {
- u32 gpdir;
- u32 gpodr;
- u32 gpdat;
- u32 gpier;
- u32 gpimr;
- u32 gpicr;
-};
-
-struct mpc85xx_gpio_data {
- /* The bank's register base in memory */
- struct ccsr_gpio __iomem *base;
- /* The address of the registers; used to identify the bank */
- ulong addr;
- /* The GPIO count of the bank */
- uint gpio_count;
- /* The GPDAT register cannot be used to determine the value of output
- * pins on MPC8572/MPC8536, so we shadow it and use the shadowed value
- * for output pins
- */
- u32 dat_shadow;
-};
-
-inline u32 gpio_mask(uint gpio)
-{
- return (1U << (31 - (gpio)));
-}
-
-static inline u32 mpc85xx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
-{
- return in_be32(&base->gpdat) & mask;
-}
-
-static inline u32 mpc85xx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
-{
- return in_be32(&base->gpdir) & mask;
-}
-
-static inline void mpc85xx_gpio_set_in(struct ccsr_gpio *base, u32 gpios)
-{
- clrbits_be32(&base->gpdat, gpios);
- /* GPDIR register 0 -> input */
- clrbits_be32(&base->gpdir, gpios);
-}
-
-static inline void mpc85xx_gpio_set_low(struct ccsr_gpio *base, u32 gpios)
-{
- clrbits_be32(&base->gpdat, gpios);
- /* GPDIR register 1 -> output */
- setbits_be32(&base->gpdir, gpios);
-}
-
-static inline void mpc85xx_gpio_set_high(struct ccsr_gpio *base, u32 gpios)
-{
- setbits_be32(&base->gpdat, gpios);
- /* GPDIR register 1 -> output */
- setbits_be32(&base->gpdir, gpios);
-}
-
-static inline int mpc85xx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
-{
- return in_be32(&base->gpodr) & mask;
-}
-
-static inline void mpc85xx_gpio_open_drain_on(struct ccsr_gpio *base, u32
- gpios)
-{
- /* GPODR register 1 -> open drain on */
- setbits_be32(&base->gpodr, gpios);
-}
-
-static inline void mpc85xx_gpio_open_drain_off(struct ccsr_gpio *base,
- u32 gpios)
-{
- /* GPODR register 0 -> open drain off (actively driven) */
- clrbits_be32(&base->gpodr, gpios);
-}
-
-static int mpc85xx_gpio_direction_input(struct udevice *dev, uint gpio)
-{
- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
-
- mpc85xx_gpio_set_in(data->base, gpio_mask(gpio));
- return 0;
-}
-
-static int mpc85xx_gpio_set_value(struct udevice *dev, uint gpio, int value)
-{
- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
-
- if (value) {
- data->dat_shadow |= gpio_mask(gpio);
- mpc85xx_gpio_set_high(data->base, gpio_mask(gpio));
- } else {
- data->dat_shadow &= ~gpio_mask(gpio);
- mpc85xx_gpio_set_low(data->base, gpio_mask(gpio));
- }
- return 0;
-}
-
-static int mpc85xx_gpio_direction_output(struct udevice *dev, uint gpio,
- int value)
-{
- return mpc85xx_gpio_set_value(dev, gpio, value);
-}
-
-static int mpc85xx_gpio_get_value(struct udevice *dev, uint gpio)
-{
- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
-
- if (!!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio))) {
- /* Output -> use shadowed value */
- return !!(data->dat_shadow & gpio_mask(gpio));
- }
-
- /* Input -> read value from GPDAT register */
- return !!mpc85xx_gpio_get_val(data->base, gpio_mask(gpio));
-}
-
-static int mpc85xx_gpio_get_open_drain(struct udevice *dev, uint gpio)
-{
- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
-
- return !!mpc85xx_gpio_open_drain_val(data->base, gpio_mask(gpio));
-}
-
-static int mpc85xx_gpio_set_open_drain(struct udevice *dev, uint gpio,
- int value)
-{
- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
-
- if (value)
- mpc85xx_gpio_open_drain_on(data->base, gpio_mask(gpio));
- else
- mpc85xx_gpio_open_drain_off(data->base, gpio_mask(gpio));
-
- return 0;
-}
-
-static int mpc85xx_gpio_get_function(struct udevice *dev, uint gpio)
-{
- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
- int dir;
-
- dir = !!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio));
- return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
-}
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-static int mpc85xx_gpio_ofdata_to_platdata(struct udevice *dev)
-{
- struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev);
- fdt_addr_t addr;
- fdt_size_t size;
-
- addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob,
- dev_of_offset(dev),
- "reg", 0, &size, false);
- plat->addr = addr;
- plat->size = size;
- plat->ngpios = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "ngpios", 32);
-
- return 0;
-}
-#endif
-
-static int mpc85xx_gpio_platdata_to_priv(struct udevice *dev)
-{
- struct mpc85xx_gpio_data *priv = dev_get_priv(dev);
- struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev);
- unsigned long size = plat->size;
-
- if (size == 0)
- size = 0x100;
-
- priv->addr = plat->addr;
- priv->base = map_sysmem(CONFIG_SYS_IMMR + plat->addr, size);
-
- if (!priv->base)
- return -ENOMEM;
-
- priv->gpio_count = plat->ngpios;
- priv->dat_shadow = 0;
-
- return 0;
-}
-
-static int mpc85xx_gpio_probe(struct udevice *dev)
-{
- struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- struct mpc85xx_gpio_data *data = dev_get_priv(dev);
- char name[32], *str;
-
- mpc85xx_gpio_platdata_to_priv(dev);
-
- snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
- str = strdup(name);
-
- if (!str)
- return -ENOMEM;
-
- uc_priv->bank_name = str;
- uc_priv->gpio_count = data->gpio_count;
-
- return 0;
-}
-
-static const struct dm_gpio_ops gpio_mpc85xx_ops = {
- .direction_input = mpc85xx_gpio_direction_input,
- .direction_output = mpc85xx_gpio_direction_output,
- .get_value = mpc85xx_gpio_get_value,
- .set_value = mpc85xx_gpio_set_value,
- .get_open_drain = mpc85xx_gpio_get_open_drain,
- .set_open_drain = mpc85xx_gpio_set_open_drain,
- .get_function = mpc85xx_gpio_get_function,
-};
-
-static const struct udevice_id mpc85xx_gpio_ids[] = {
- { .compatible = "fsl,pq3-gpio" },
- { /* sentinel */ }
-};
-
-U_BOOT_DRIVER(gpio_mpc85xx) = {
- .name = "gpio_mpc85xx",
- .id = UCLASS_GPIO,
- .ops = &gpio_mpc85xx_ops,
-#if CONFIG_IS_ENABLED(OF_CONTROL)
- .ofdata_to_platdata = mpc85xx_gpio_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct mpc85xx_gpio_plat),
- .of_match = mpc85xx_gpio_ids,
-#endif
- .probe = mpc85xx_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct mpc85xx_gpio_data),
-};
diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c
new file mode 100644
index 0000000000..0aa72ecd9f
--- /dev/null
+++ b/drivers/gpio/mpc8xxx_gpio.c
@@ -0,0 +1,274 @@
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, six at gdsys.de
+ *
+ * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
+ *
+ * Copyright 2010 eXMeritus, A Boeing Company
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mapmem.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ccsr_gpio {
+ u32 gpdir;
+ u32 gpodr;
+ u32 gpdat;
+ u32 gpier;
+ u32 gpimr;
+ u32 gpicr;
+};
+
+struct mpc8xxx_gpio_data {
+ /* The bank's register base in memory */
+ struct ccsr_gpio __iomem *base;
+ /* The address of the registers; used to identify the bank */
+ ulong addr;
+ /* The GPIO count of the bank */
+ uint gpio_count;
+ /* The GPDAT register cannot be used to determine the value of output
+ * pins on MPC8572/MPC8536, so we shadow it and use the shadowed value
+ * for output pins
+ */
+ u32 dat_shadow;
+ ulong type;
+};
+
+enum {
+ MPC8XXX_GPIO_TYPE,
+ MPC5121_GPIO_TYPE,
+};
+
+inline u32 gpio_mask(uint gpio)
+{
+ return (1U << (31 - (gpio)));
+}
+
+static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
+{
+ return in_be32(&base->gpdat) & mask;
+}
+
+static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
+{
+ return in_be32(&base->gpdir) & mask;
+}
+
+static inline void mpc8xxx_gpio_set_in(struct ccsr_gpio *base, u32 gpios)
+{
+ clrbits_be32(&base->gpdat, gpios);
+ /* GPDIR register 0 -> input */
+ clrbits_be32(&base->gpdir, gpios);
+}
+
+static inline void mpc8xxx_gpio_set_low(struct ccsr_gpio *base, u32 gpios)
+{
+ clrbits_be32(&base->gpdat, gpios);
+ /* GPDIR register 1 -> output */
+ setbits_be32(&base->gpdir, gpios);
+}
+
+static inline void mpc8xxx_gpio_set_high(struct ccsr_gpio *base, u32 gpios)
+{
+ setbits_be32(&base->gpdat, gpios);
+ /* GPDIR register 1 -> output */
+ setbits_be32(&base->gpdir, gpios);
+}
+
+static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
+{
+ return in_be32(&base->gpodr) & mask;
+}
+
+static inline void mpc8xxx_gpio_open_drain_on(struct ccsr_gpio *base, u32
+ gpios)
+{
+ /* GPODR register 1 -> open drain on */
+ setbits_be32(&base->gpodr, gpios);
+}
+
+static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base,
+ u32 gpios)
+{
+ /* GPODR register 0 -> open drain off (actively driven) */
+ clrbits_be32(&base->gpodr, gpios);
+}
+
+static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
+{
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+ mpc8xxx_gpio_set_in(data->base, gpio_mask(gpio));
+ return 0;
+}
+
+static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value)
+{
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+ if (value) {
+ data->dat_shadow |= gpio_mask(gpio);
+ mpc8xxx_gpio_set_high(data->base, gpio_mask(gpio));
+ } else {
+ data->dat_shadow &= ~gpio_mask(gpio);
+ mpc8xxx_gpio_set_low(data->base, gpio_mask(gpio));
+ }
+ return 0;
+}
+
+static int mpc8xxx_gpio_direction_output(struct udevice *dev, uint gpio,
+ int value)
+{
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+ /* GPIO 28..31 are input only on MPC5121 */
+ if (data->type == MPC5121_GPIO_TYPE && gpio >= 28)
+ return -EINVAL;
+
+ return mpc8xxx_gpio_set_value(dev, gpio, value);
+}
+
+static int mpc8xxx_gpio_get_value(struct udevice *dev, uint gpio)
+{
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+ if (!!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio))) {
+ /* Output -> use shadowed value */
+ return !!(data->dat_shadow & gpio_mask(gpio));
+ }
+
+ /* Input -> read value from GPDAT register */
+ return !!mpc8xxx_gpio_get_val(data->base, gpio_mask(gpio));
+}
+
+static int mpc8xxx_gpio_get_open_drain(struct udevice *dev, uint gpio)
+{
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+ return !!mpc8xxx_gpio_open_drain_val(data->base, gpio_mask(gpio));
+}
+
+static int mpc8xxx_gpio_set_open_drain(struct udevice *dev, uint gpio,
+ int value)
+{
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+
+ if (value)
+ mpc8xxx_gpio_open_drain_on(data->base, gpio_mask(gpio));
+ else
+ mpc8xxx_gpio_open_drain_off(data->base, gpio_mask(gpio));
+
+ return 0;
+}
+
+static int mpc8xxx_gpio_get_function(struct udevice *dev, uint gpio)
+{
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+ int dir;
+
+ dir = !!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio));
+ return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
+}
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev)
+{
+ struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
+ fdt_addr_t addr;
+ fdt_size_t size;
+
+ addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob,
+ dev_of_offset(dev),
+ "reg", 0, &size, false);
+ plat->addr = addr;
+ plat->size = size;
+ plat->ngpios = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "ngpios", 32);
+
+ return 0;
+}
+#endif
+
+static int mpc8xxx_gpio_platdata_to_priv(struct udevice *dev)
+{
+ struct mpc8xxx_gpio_data *priv = dev_get_priv(dev);
+ struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
+ unsigned long size = plat->size;
+ ulong driver_data = dev_get_driver_data(dev);
+
+ if (size == 0)
+ size = 0x100;
+
+ priv->addr = plat->addr;
+ priv->base = map_sysmem(CONFIG_SYS_IMMR + plat->addr, size);
+
+ if (!priv->base)
+ return -ENOMEM;
+
+ priv->gpio_count = plat->ngpios;
+ priv->dat_shadow = 0;
+
+ priv->type = driver_data;
+
+ return 0;
+}
+
+static int mpc8xxx_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+ char name[32], *str;
+
+ mpc8xxx_gpio_platdata_to_priv(dev);
+
+ snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
+ str = strdup(name);
+
+ if (!str)
+ return -ENOMEM;
+
+ uc_priv->bank_name = str;
+ uc_priv->gpio_count = data->gpio_count;
+
+ return 0;
+}
+
+static const struct dm_gpio_ops gpio_mpc8xxx_ops = {
+ .direction_input = mpc8xxx_gpio_direction_input,
+ .direction_output = mpc8xxx_gpio_direction_output,
+ .get_value = mpc8xxx_gpio_get_value,
+ .set_value = mpc8xxx_gpio_set_value,
+ .get_open_drain = mpc8xxx_gpio_get_open_drain,
+ .set_open_drain = mpc8xxx_gpio_set_open_drain,
+ .get_function = mpc8xxx_gpio_get_function,
+};
+
+static const struct udevice_id mpc8xxx_gpio_ids[] = {
+ { .compatible = "fsl,pq3-gpio", .data = MPC8XXX_GPIO_TYPE },
+ { .compatible = "fsl,mpc8308-gpio", .data = MPC8XXX_GPIO_TYPE },
+ { .compatible = "fsl,mpc8349-gpio", .data = MPC8XXX_GPIO_TYPE },
+ { .compatible = "fsl,mpc8572-gpio", .data = MPC8XXX_GPIO_TYPE},
+ { .compatible = "fsl,mpc8610-gpio", .data = MPC8XXX_GPIO_TYPE},
+ { .compatible = "fsl,mpc5121-gpio", .data = MPC5121_GPIO_TYPE, },
+ { .compatible = "fsl,qoriq-gpio", .data = MPC8XXX_GPIO_TYPE },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(gpio_mpc8xxx) = {
+ .name = "gpio_mpc8xxx",
+ .id = UCLASS_GPIO,
+ .ops = &gpio_mpc8xxx_ops,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ .ofdata_to_platdata = mpc8xxx_gpio_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct mpc8xxx_gpio_plat),
+ .of_match = mpc8xxx_gpio_ids,
+#endif
+ .probe = mpc8xxx_gpio_probe,
+ .priv_auto_alloc_size = sizeof(struct mpc8xxx_gpio_data),
+};
--
2.11.0
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