[U-Boot] [PATCH 32/51] drivers: Add ihs_fpga and gdsys_soc drivers
Mario Six
mario.six at gdsys.cc
Fri Jul 14 12:55:18 UTC 2017
This patch adds DM drivers for IHS FPGAs and their associated busses, as
well as uclasses for both.
Signed-off-by: Mario Six <mario.six at gdsys.cc>
---
drivers/misc/Kconfig | 6 +
drivers/misc/Makefile | 1 +
drivers/misc/gdsys_soc.c | 51 +++
drivers/misc/ihs_fpga.c | 871 +++++++++++++++++++++++++++++++++++++++++++++++
include/dm/uclass-id.h | 2 +
include/gdsys_soc.h | 29 ++
include/ihs_fpga.h | 111 ++++++
7 files changed, 1071 insertions(+)
create mode 100644 drivers/misc/gdsys_soc.c
create mode 100644 drivers/misc/ihs_fpga.c
create mode 100644 include/gdsys_soc.h
create mode 100644 include/ihs_fpga.h
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index d1ddbbe157..8b59a444ce 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -196,4 +196,10 @@ config I2C_EEPROM
depends on MISC
help
Enable a generic driver for EEPROMs attached via I2C.
+
+config IHS_FPGA
+ bool "Enable IHS FPGA driver"
+ depends on MISC
+ help
+ Support for IHS FPGA.
endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 10265c8fb4..d2e46fc7d6 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -52,3 +52,4 @@ obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
obj-$(CONFIG_QFW) += qfw.o
obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
+obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o gdsys_soc.o
diff --git a/drivers/misc/gdsys_soc.c b/drivers/misc/gdsys_soc.c
new file mode 100644
index 0000000000..34b06d44bd
--- /dev/null
+++ b/drivers/misc/gdsys_soc.c
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2017
+ * Mario Six, Guntermann & Drunck GmbH, mario.six at gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <gdsys_soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int gdsys_soc_child_post_bind(struct udevice *dev)
+{
+ struct gdsys_soc_child_platdata *pplat = dev_get_parent_platdata(dev);
+ struct udevice *fpga;
+
+ if (uclass_get_device_by_phandle(UCLASS_IHS_FPGA, dev->parent, "fpga",
+ &fpga)) {
+ printf("%s: Could not find 'fpga' phandle.\n",
+ dev->parent->name);
+ return 1;
+ }
+
+ pplat->fpga = fpga;
+
+ return 0;
+}
+
+UCLASS_DRIVER(gdsys_soc) = {
+ .id = UCLASS_GDSYS_SOC,
+ .name = "gdsys_soc",
+ .post_probe = dm_scan_fdt_dev,
+ .child_post_bind = gdsys_soc_child_post_bind,
+ .per_child_platdata_auto_alloc_size =
+ sizeof(struct gdsys_soc_child_platdata),
+};
+
+static const struct udevice_id gdsys_soc_ids[] = {
+ { .compatible = "gdsys,soc" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(gdsys_soc_bus) = {
+ .name = "gdsys_soc_bus",
+ .id = UCLASS_GDSYS_SOC,
+ .of_match = gdsys_soc_ids,
+};
diff --git a/drivers/misc/ihs_fpga.c b/drivers/misc/ihs_fpga.c
new file mode 100644
index 0000000000..a2b5d3f58c
--- /dev/null
+++ b/drivers/misc/ihs_fpga.c
@@ -0,0 +1,871 @@
+/*
+ * (C) Copyright 2017
+ * Mario Six, Guntermann & Drunck GmbH, mario.six at gdsys.cc
+ *
+ * based on the ioep-fpga driver, which is
+ *
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach at gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+#include <dm/lists.h>
+#include <ihs_fpga.h>
+#include <misc.h>
+#include <mapmem.h>
+#include <asm/gpio.h>
+#include <linux/bitops.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct reg_spec {
+ uint addr;
+ uint shift;
+ ulong mask;
+};
+
+struct ihs_fpga_priv {
+ u8 *regs;
+ fdt_addr_t addr;
+ struct gpio_desc reset_gpio;
+ struct gpio_desc done_gpio;
+ struct gpio_desc startupfin_gpios[2];
+ int regmap_node;
+ bool has_osd;
+};
+
+const u16 reflection_testpattern = 0xdede;
+
+enum pcb_video_type {
+ PCB_DVI_SL,
+ PCB_DP_165MPIX,
+ PCB_DP_300MPIX,
+ PCB_HDMI,
+ PCB_DP_1_2,
+ PCB_HDMI_2_0,
+};
+
+enum pcb_transmission_type {
+ PCB_CAT_1G,
+ PCB_FIBER_3G,
+ PCB_CAT_10G,
+ PCB_FIBER_10G,
+};
+
+enum carrier_speed {
+ CARRIER_SPEED_1G,
+ CARRIER_SPEED_3G,
+ CARRIER_SPEED_2_5G = CARRIER_SPEED_3G,
+ CARRIER_SPEED_10G,
+};
+
+enum ram_config {
+ RAM_DDR2_32BIT_295MBPS,
+ RAM_DDR3_32BIT_590MBPS,
+ RAM_DDR3_48BIT_590MBPS,
+ RAM_DDR3_64BIT_1800MBPS,
+ RAM_DDR3_48BIT_1800MBPS,
+};
+
+enum sysclock {
+ SYSCLK_147456,
+};
+
+struct fpga_versions {
+ bool video_channel;
+ bool con_side;
+ enum pcb_video_type pcb_video_type;
+ enum pcb_transmission_type pcb_transmission_type;
+ unsigned int hw_version;
+};
+
+struct fpga_features {
+ u8 video_channels;
+ u8 carriers;
+ enum carrier_speed carrier_speed;
+ enum ram_config ram_config;
+ enum sysclock sysclock;
+
+ bool pcm_tx;
+ bool pcm_rx;
+ bool spdif_tx;
+ bool spdif_rx;
+ bool usb2;
+ bool rs232;
+ bool compression_type1;
+ bool compression_type2;
+ bool compression_type3;
+ bool interlace;
+ bool osd;
+ bool compression_pipes;
+};
+
+int fpga_set_reg(struct udevice *dev, const char *compat,
+ uint value)
+{
+ struct ihs_fpga_ops *ops = ihs_fpga_get_ops(dev);
+
+ return ops->set_reg(dev, compat, value);
+}
+
+int fpga_get_reg(struct udevice *dev, const char *compat,
+ uint *value)
+{
+ struct ihs_fpga_ops *ops = ihs_fpga_get_ops(dev);
+
+ return ops->get_reg(dev, compat, value);
+}
+
+u16 fpga_in_le16(struct udevice *dev, phys_addr_t addr)
+{
+ struct ihs_fpga_ops *ops = ihs_fpga_get_ops(dev);
+
+ return ops->in_le16(dev, addr);
+}
+
+void fpga_out_le16(struct udevice *dev, phys_addr_t addr, u16 value)
+{
+ struct ihs_fpga_ops *ops = ihs_fpga_get_ops(dev);
+
+ return ops->out_le16(dev, addr, value);
+}
+
+#ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM
+
+static int get_versions(struct udevice *dev, struct fpga_versions *versions)
+{
+ enum {
+ VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12),
+ VERSIONS_FPGA_CON_SIDE = BIT(13),
+ VERSIONS_FPGA_SC = BIT(14),
+ VERSIONS_PCB_CON = BIT(9),
+ VERSIONS_PCB_SC = BIT(8),
+ VERSIONS_PCB_VIDEO_MASK = 0x3 << 6,
+ VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6,
+ VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6,
+ VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4,
+ VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4,
+ VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4,
+ VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4,
+ VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4,
+ VERSIONS_HW_VER_MASK = 0xf << 0,
+ };
+ uint raw_versions;
+
+ memset(versions, 0, sizeof(struct fpga_versions));
+
+ fpga_get_reg(dev, "versions", &raw_versions);
+
+ versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL;
+ versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE;
+
+ switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) {
+ case VERSIONS_PCB_VIDEO_DP_1_2:
+ versions->pcb_video_type = PCB_DP_1_2;
+ break;
+
+ case VERSIONS_PCB_VIDEO_HDMI_2_0:
+ versions->pcb_video_type = PCB_HDMI_2_0;
+ break;
+ }
+
+ switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) {
+ case VERSIONS_PCB_TRANSMISSION_FIBER_10G:
+ versions->pcb_transmission_type = PCB_FIBER_10G;
+ break;
+
+ case VERSIONS_PCB_TRANSMISSION_CAT_10G:
+ versions->pcb_transmission_type = PCB_CAT_10G;
+ break;
+
+ case VERSIONS_PCB_TRANSMISSION_FIBER_3G:
+ versions->pcb_transmission_type = PCB_FIBER_3G;
+ break;
+
+ case VERSIONS_PCB_TRANSMISSION_CAT_1G:
+ versions->pcb_transmission_type = PCB_CAT_1G;
+ break;
+ }
+
+ versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
+
+ return 0;
+}
+
+static int get_features(struct udevice *dev, struct fpga_features *features)
+{
+ enum {
+ FEATURE_SPDIF_RX = BIT(15),
+ FEATURE_SPDIF_TX = BIT(14),
+ FEATURE_PCM_RX = BIT(13),
+ FEATURE_PCM_TX = BIT(12),
+ FEATURE_RAM_MASK = GENMASK(11, 8),
+ FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8,
+ FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8,
+ FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8,
+ FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8,
+ FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8,
+ FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6),
+ FEATURE_CARRIER_SPEED_1G = 0x0 << 6,
+ FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6,
+ FEATURE_CARRIER_SPEED_10G = 0x2 << 6,
+ FEATURE_CARRIERS_MASK = GENMASK(5, 4),
+ FEATURE_CARRIERS_0 = 0x0 << 4,
+ FEATURE_CARRIERS_1 = 0x1 << 4,
+ FEATURE_CARRIERS_2 = 0x2 << 4,
+ FEATURE_CARRIERS_4 = 0x3 << 4,
+ FEATURE_USB2 = BIT(3),
+ FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0),
+ FEATURE_VIDEOCHANNELS_0 = 0x0 << 0,
+ FEATURE_VIDEOCHANNELS_1 = 0x1 << 0,
+ FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0,
+ FEATURE_VIDEOCHANNELS_2 = 0x3 << 0,
+ };
+
+ enum {
+ EXT_FEATURE_OSD = BIT(15),
+ EXT_FEATURE_ETHERNET = BIT(9),
+ EXT_FEATURE_INTERLACE = BIT(8),
+ EXT_FEATURE_RS232 = BIT(7),
+ EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4),
+ EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4,
+ EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4,
+ EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4,
+ EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0),
+ EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1),
+ EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2),
+ };
+
+ uint raw_features;
+ uint raw_extended_features;
+
+ memset(features, 0, sizeof(struct fpga_features));
+
+ fpga_get_reg(dev, "fpga-features", &raw_features);
+ fpga_get_reg(dev, "fpga-ext-features", &raw_extended_features);
+
+ switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) {
+ case FEATURE_VIDEOCHANNELS_0:
+ features->video_channels = 0;
+ break;
+
+ case FEATURE_VIDEOCHANNELS_1:
+ features->video_channels = 1;
+ break;
+
+ case FEATURE_VIDEOCHANNELS_1_1:
+ case FEATURE_VIDEOCHANNELS_2:
+ features->video_channels = 2;
+ break;
+ };
+
+ switch (raw_features & FEATURE_CARRIERS_MASK) {
+ case FEATURE_CARRIERS_0:
+ features->carriers = 0;
+ break;
+
+ case FEATURE_CARRIERS_1:
+ features->carriers = 1;
+ break;
+
+ case FEATURE_CARRIERS_2:
+ features->carriers = 2;
+ break;
+
+ case FEATURE_CARRIERS_4:
+ features->carriers = 4;
+ break;
+ }
+
+ switch (raw_features & FEATURE_CARRIER_SPEED_MASK) {
+ case FEATURE_CARRIER_SPEED_1G:
+ features->carrier_speed = CARRIER_SPEED_1G;
+ break;
+ case FEATURE_CARRIER_SPEED_2_5G:
+ features->carrier_speed = CARRIER_SPEED_2_5G;
+ break;
+ case FEATURE_CARRIER_SPEED_10G:
+ features->carrier_speed = CARRIER_SPEED_10G;
+ break;
+ }
+
+ switch (raw_features & FEATURE_RAM_MASK) {
+ case FEATURE_RAM_DDR2_32BIT_295MBPS:
+ features->ram_config = RAM_DDR2_32BIT_295MBPS;
+ break;
+
+ case FEATURE_RAM_DDR3_32BIT_590MBPS:
+ features->ram_config = RAM_DDR3_32BIT_590MBPS;
+ break;
+
+ case FEATURE_RAM_DDR3_48BIT_590MBPS:
+ features->ram_config = RAM_DDR3_48BIT_590MBPS;
+ break;
+
+ case FEATURE_RAM_DDR3_64BIT_1800MBPS:
+ features->ram_config = RAM_DDR3_64BIT_1800MBPS;
+ break;
+
+ case FEATURE_RAM_DDR3_48BIT_1800MBPS:
+ features->ram_config = RAM_DDR3_48BIT_1800MBPS;
+ break;
+ }
+
+ features->pcm_tx = raw_features & FEATURE_PCM_TX;
+ features->pcm_rx = raw_features & FEATURE_PCM_RX;
+ features->spdif_tx = raw_features & FEATURE_SPDIF_TX;
+ features->spdif_rx = raw_features & FEATURE_SPDIF_RX;
+ features->usb2 = raw_features & FEATURE_USB2;
+ features->rs232 = raw_extended_features & EXT_FEATURE_RS232;
+ features->compression_type1 = raw_extended_features &
+ EXT_FEATURE_COMPRESSION_TYPE1;
+ features->compression_type2 = raw_extended_features &
+ EXT_FEATURE_COMPRESSION_TYPE2;
+ features->compression_type3 = raw_extended_features &
+ EXT_FEATURE_COMPRESSION_TYPE3;
+ features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE;
+ features->osd = raw_extended_features & EXT_FEATURE_OSD;
+ features->compression_pipes = raw_extended_features &
+ EXT_FEATURE_COMPRESSION_PERF_MASK;
+
+ return 0;
+}
+
+#else
+
+static int get_versions(unsigned int fpga, struct fpga_versions *versions)
+{
+ enum {
+ /* HW version encoding is a mess, leave it for the moment */
+ VERSIONS_HW_VER_MASK = 0xf << 0,
+ VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4),
+ VERSIONS_SFP = BIT(5),
+ VERSIONS_VIDEO_MASK = 0x7 << 6,
+ VERSIONS_VIDEO_DVI = 0x0 << 6,
+ VERSIONS_VIDEO_DP_165 = 0x1 << 6,
+ VERSIONS_VIDEO_DP_300 = 0x2 << 6,
+ VERSIONS_VIDEO_HDMI = 0x3 << 6,
+ VERSIONS_UT_MASK = 0xf << 12,
+ VERSIONS_UT_MAIN_SERVER = 0x0 << 12,
+ VERSIONS_UT_MAIN_USER = 0x1 << 12,
+ VERSIONS_UT_VIDEO_SERVER = 0x2 << 12,
+ VERSIONS_UT_VIDEO_USER = 0x3 << 12,
+ };
+ u16 raw_versions;
+
+ memset(versions, 0, sizeof(struct fpga_versions));
+
+ FPGA_GET_REG(fpga, versions, &raw_versions);
+
+ switch (raw_versions & VERSIONS_UT_MASK) {
+ case VERSIONS_UT_MAIN_SERVER:
+ versions->video_channel = false;
+ versions->con_side = false;
+ break;
+
+ case VERSIONS_UT_MAIN_USER:
+ versions->video_channel = false;
+ versions->con_side = true;
+ break;
+
+ case VERSIONS_UT_VIDEO_SERVER:
+ versions->video_channel = true;
+ versions->con_side = false;
+ break;
+
+ case VERSIONS_UT_VIDEO_USER:
+ versions->video_channel = true;
+ versions->con_side = true;
+ break;
+ }
+
+ switch (raw_versions & VERSIONS_VIDEO_MASK) {
+ case VERSIONS_VIDEO_DVI:
+ versions->pcb_video_type = PCB_DVI_SL;
+ break;
+
+ case VERSIONS_VIDEO_DP_165:
+ versions->pcb_video_type = PCB_DP_165MPIX;
+ break;
+
+ case VERSIONS_VIDEO_DP_300:
+ versions->pcb_video_type = PCB_DP_300MPIX;
+ break;
+
+ case VERSIONS_VIDEO_HDMI:
+ versions->pcb_video_type = PCB_HDMI;
+ break;
+ }
+
+ versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;
+
+ if (raw_versions & VERSIONS_SFP)
+ versions->pcb_transmission_type = PCB_FIBER_3G;
+ else
+ versions->pcb_transmission_type = PCB_CAT_1G;
+
+ return 0;
+}
+
+static int get_features(unsigned int fpga, struct fpga_features *features)
+{
+ enum {
+ FEATURE_CARRIER_SPEED_2_5 = BIT(4),
+ FEATURE_RAM_MASK = 0x7 << 5,
+ FEATURE_RAM_DDR2_32BIT = 0x0 << 5,
+ FEATURE_RAM_DDR3_32BIT = 0x1 << 5,
+ FEATURE_RAM_DDR3_48BIT = 0x2 << 5,
+ FEATURE_PCM_AUDIO_TX = BIT(9),
+ FEATURE_PCM_AUDIO_RX = BIT(10),
+ FEATURE_OSD = BIT(11),
+ FEATURE_USB20 = BIT(12),
+ FEATURE_COMPRESSION_MASK = 7 << 13,
+ FEATURE_COMPRESSION_TYPE1 = 0x1 << 13,
+ FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13,
+ FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13,
+ };
+
+ enum {
+ EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0),
+ EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1),
+ EXTENDED_FEATURE_RS232 = BIT(2),
+ EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3),
+ EXTENDED_FEATURE_INTERLACE = BIT(4),
+ };
+
+ u16 raw_features;
+ u16 raw_extended_features;
+
+ memset(features, 0, sizeof(struct fpga_features));
+
+ FPGA_GET_REG(fpga, fpga_features, &raw_features);
+ FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features);
+
+ features->video_channels = raw_features & 0x3;
+ features->carriers = (raw_features >> 2) & 0x3;
+
+ features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5)
+ ? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G;
+
+ switch (raw_features & FEATURE_RAM_MASK) {
+ case FEATURE_RAM_DDR2_32BIT:
+ features->ram_config = RAM_DDR2_32BIT_295MBPS;
+ break;
+
+ case FEATURE_RAM_DDR3_32BIT:
+ features->ram_config = RAM_DDR3_32BIT_590MBPS;
+ break;
+
+ case FEATURE_RAM_DDR3_48BIT:
+ features->ram_config = RAM_DDR3_48BIT_590MBPS;
+ break;
+ }
+
+ features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX;
+ features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX;
+ features->spdif_tx = raw_extended_features &
+ EXTENDED_FEATURE_SPDIF_AUDIO_TX;
+ features->spdif_rx = raw_extended_features &
+ EXTENDED_FEATURE_SPDIF_AUDIO_RX;
+
+ features->usb2 = raw_features & FEATURE_USB20;
+ features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232;
+
+ features->compression_type1 = false;
+ features->compression_type2 = false;
+ features->compression_type3 = false;
+ switch (raw_features & FEATURE_COMPRESSION_MASK) {
+ case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3:
+ features->compression_type3 = true;
+ case FEATURE_COMPRESSION_TYPE1_TYPE2:
+ features->compression_type2 = true;
+ case FEATURE_COMPRESSION_TYPE1:
+ features->compression_type1 = true;
+ break;
+ }
+
+ features->interlace = raw_extended_features &
+ EXTENDED_FEATURE_INTERLACE;
+ features->osd = raw_features & FEATURE_OSD;
+ features->compression_pipes = raw_extended_features &
+ EXTENDED_FEATURE_COMPRESSION_PIPES;
+
+ return 0;
+}
+
+#endif
+
+static void fpga_print_info(struct udevice *dev)
+{
+ struct ihs_fpga_priv *priv = dev_get_priv(dev);
+ uint fpga_version;
+ struct fpga_versions versions;
+ struct fpga_features features;
+
+ fpga_get_reg(dev, "fpga-version", &fpga_version);
+ get_versions(dev, &versions);
+ get_features(dev, &features);
+
+ priv->has_osd = features.osd;
+
+ if (versions.video_channel)
+ printf("Videochannel");
+ else
+ printf("Mainchannel");
+
+ if (versions.con_side)
+ printf(" User");
+ else
+ printf(" Server");
+
+// FIXME
+#if 0
+ if (versions & (1<<4))
+ printf(" UC");
+#endif
+
+ switch (versions.pcb_transmission_type) {
+ case PCB_CAT_1G:
+ case PCB_CAT_10G:
+ printf(" CAT");
+ break;
+ case PCB_FIBER_3G:
+ case PCB_FIBER_10G:
+ printf(" Fiber");
+ break;
+ };
+
+ switch (versions.pcb_video_type) {
+ case PCB_DVI_SL:
+ printf(" DVI,");
+ break;
+ case PCB_DP_165MPIX:
+ printf(" DP 165MPix/s,");
+ break;
+ case PCB_DP_300MPIX:
+ printf(" DP 300MPix/s,");
+ break;
+ case PCB_HDMI:
+ printf(" HDMI,");
+ break;
+ case PCB_DP_1_2:
+ printf(" DP 1.2,");
+ break;
+ case PCB_HDMI_2_0:
+ printf(" HDMI 2.0,");
+ break;
+ }
+
+ printf(" FPGA V %d.%02d\n features: ",
+ fpga_version / 100, fpga_version % 100);
+
+ if (!features.compression_type1 &&
+ !features.compression_type2 &&
+ !features.compression_type3)
+ printf("no compression, ");
+
+ if (features.compression_type1)
+ printf("type1-deltacompression, ");
+
+ if (features.compression_type2)
+ printf("type2-inlinecompression, ");
+
+ if (features.compression_type3)
+ printf("type3-intempocompression, ");
+
+ printf("%sosd", features.osd ? "" : "no ");
+
+ if (features.pcm_rx && features.pcm_tx)
+ printf(", pcm rx+tx");
+ else if (features.pcm_rx)
+ printf(", pcm rx");
+ else if (features.pcm_tx)
+ printf(", pcm tx");
+
+ if (features.spdif_rx && features.spdif_tx)
+ printf(", spdif rx+tx");
+ else if (features.spdif_rx)
+ printf(", spdif rx");
+ else if (features.spdif_tx)
+ printf(", spdif tx");
+
+ puts(",\n ");
+
+ switch (features.sysclock) {
+ case SYSCLK_147456:
+ printf("clock 147.456 MHz");
+ break;
+ }
+
+ switch (features.ram_config) {
+ case RAM_DDR2_32BIT_295MBPS:
+ printf(", RAM 32 bit DDR2");
+ break;
+ case RAM_DDR3_32BIT_590MBPS:
+ printf(", RAM 32 bit DDR3");
+ break;
+ case RAM_DDR3_48BIT_590MBPS:
+ case RAM_DDR3_48BIT_1800MBPS:
+ printf(", RAM 48 bit DDR3");
+ break;
+ case RAM_DDR3_64BIT_1800MBPS:
+ printf(", RAM 64 bit DDR3");
+ break;
+ }
+
+ printf(", %d carrier(s)", features.carriers);
+
+ switch (features.carrier_speed) {
+ case CARRIER_SPEED_1G:
+ printf(", 1Gbit/s");
+ break;
+ case CARRIER_SPEED_3G:
+ printf(", 3Gbit/s");
+ break;
+ case CARRIER_SPEED_10G:
+ printf(", 10Gbit/s");
+ break;
+ }
+
+ printf(", %d video channel(s)\n", features.video_channels);
+}
+
+static void signal_startup_finished(struct udevice *dev)
+{
+ struct ihs_fpga_priv *priv = dev_get_priv(dev);
+
+ gpio_request_list_by_name(dev, "startupfin-gpios",
+ priv->startupfin_gpios, 2, GPIOD_IS_OUT);
+ if (!priv->startupfin_gpios[0].dev) {
+ printf("%s: Could not get startupfin-GPIOs.\n", dev->name);
+ return;
+ }
+
+ /* Inverted */
+ dm_gpio_set_value(&priv->startupfin_gpios[0], 0);
+ /* Non-inverted */
+ dm_gpio_set_value(&priv->startupfin_gpios[1], 1);
+}
+
+static int do_reflection_test(struct udevice *dev)
+{
+ int ctr = 0;
+
+ while (1) {
+ uint val;
+
+ fpga_set_reg(dev, "reflection-low", reflection_testpattern);
+
+ fpga_get_reg(dev, "reflection-low", &val);
+ if (val == (~reflection_testpattern & 0xffff))
+ return 1;
+
+ mdelay(100);
+ if (ctr++ > 5)
+ return 0;
+ }
+}
+
+UCLASS_DRIVER(ihs_fpga) = {
+ .id = UCLASS_IHS_FPGA,
+ .name = "ihs_fpga",
+ .flags = DM_UC_FLAG_SEQ_ALIAS,
+};
+
+static int get_reg_spec(struct udevice *dev, const char *compat,
+ struct reg_spec *spec)
+{
+ struct ihs_fpga_priv *priv = dev_get_priv(dev);
+ int childnode;
+
+ fdt_for_each_subnode(childnode, gd->fdt_blob, priv->regmap_node) {
+ const struct fdt_property *compatprop;
+ u32 reg[3];
+ uint start_bit, end_bit;
+
+ compatprop = fdt_get_property(gd->fdt_blob, childnode,
+ "compatible", NULL);
+
+ if (!strcmp(compatprop->data, compat)) {
+ fdtdec_get_int_array(gd->fdt_blob, childnode, "reg",
+ reg, 3);
+ start_bit = reg[1];
+ end_bit = reg[1] - reg[2] + 1;
+
+ spec->mask = GENMASK(start_bit, end_bit);
+ spec->addr = reg[0];
+ spec->shift = end_bit;
+
+ return 0;
+ }
+ }
+
+ return 1;
+}
+
+static int ihs_fpga_set_reg(struct udevice *dev, const char *compat,
+ uint value)
+{
+ struct ihs_fpga_priv *priv = dev_get_priv(dev);
+ struct reg_spec spec;
+
+ if (get_reg_spec(dev, compat, &spec)) {
+ printf("%s: Could not get %s regspec for '%s'.\n", __func__,
+ dev->name, compat);
+ return -ENODEV;
+ }
+
+ out_le16((void *)(priv->regs + spec.addr), value << spec.shift);
+
+ return 0;
+}
+
+static int ihs_fpga_get_reg(struct udevice *dev, const char *compat,
+ uint *value)
+{
+ struct ihs_fpga_priv *priv = dev_get_priv(dev);
+ struct reg_spec spec;
+ uint tmp;
+
+ if (get_reg_spec(dev, compat, &spec)) {
+ printf("%s: Could not get %s regspec for '%s'.\n", __func__,
+ dev->name, compat);
+ return -ENODEV;
+ }
+
+ tmp = in_le16((void *)(priv->regs + spec.addr));
+ *value = (tmp & spec.mask) >> spec.shift;
+
+ return 0;
+}
+
+static u16 ihs_fpga_in_le16(struct udevice *dev, phys_addr_t addr)
+{
+ struct ihs_fpga_priv *priv = dev_get_priv(dev);
+
+ /* TODO: MCLink transfer */
+
+ return in_le16((void *)(priv->regs + addr));
+}
+
+static void ihs_fpga_out_le16(struct udevice *dev, phys_addr_t addr, u16 value)
+{
+ struct ihs_fpga_priv *priv = dev_get_priv(dev);
+
+ /* TODO: MCLink transfer */
+
+ out_le16((void *)(priv->regs + addr), value);
+}
+
+static const struct ihs_fpga_ops ihs_fpga_ops = {
+ .set_reg = ihs_fpga_set_reg,
+ .get_reg = ihs_fpga_get_reg,
+ .in_le16 = ihs_fpga_in_le16,
+ .out_le16 = ihs_fpga_out_le16,
+};
+
+static int ihs_fpga_probe(struct udevice *dev)
+{
+ struct ihs_fpga_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+ struct fdtdec_phandle_args phandle_args;
+ struct fdtdec_phandle_args args;
+ struct udevice *busdev = NULL;
+ struct udevice *child = NULL;
+ uint mem_width;
+
+ if (fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
+ "regmap", NULL, 0, 0, &args)) {
+ printf("%s: Could not get regmap.\n", dev->name);
+ return 1;
+ }
+
+ priv->regmap_node = args.node;
+
+ addr = devfdt_get_addr(dev);
+
+ priv->addr = addr;
+ priv->regs = map_sysmem(addr, mem_width);
+
+ gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio,
+ GPIOD_IS_OUT);
+ if (!priv->reset_gpio.dev)
+ printf("%s: Could not get reset-GPIO.\n", dev->name);
+
+ gpio_request_by_name(dev, "done-gpios", 0, &priv->done_gpio,
+ GPIOD_IS_IN);
+ if (!priv->done_gpio.dev)
+ printf("%s: Could not get done-GPIO.\n", dev->name);
+
+ dm_gpio_set_value(&priv->reset_gpio, 1);
+
+ signal_startup_finished(dev);
+
+ if (!do_reflection_test(dev)) {
+ int ctr = 0;
+
+ dm_gpio_set_value(&priv->reset_gpio, 0);
+
+ while (!dm_gpio_get_value(&priv->done_gpio)) {
+ mdelay(100);
+ if (ctr++ > 5) {
+ printf("Initializing FPGA failed\n");
+ break;
+ }
+ }
+
+ udelay(10);
+
+ dm_gpio_set_value(&priv->reset_gpio, 1);
+
+ if (!do_reflection_test(dev)) {
+ printf("%s: Reflection test FAILED.\n", dev->name);
+ return -1;
+ }
+ }
+
+ printf("%s: Reflection test passed.\n", dev->name);
+
+ if (fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev), "bus",
+ NULL, 0, 0, &phandle_args))
+ return -1;
+
+ lists_bind_fdt(dev, offset_to_ofnode(phandle_args.node), &busdev);
+
+ fpga_print_info(dev);
+
+ /* TODO: Check if this should be gazerbeam-specific */
+ if (priv->has_osd) {
+ /* Disable softcore, select external pixclock */
+ fpga_set_reg(dev, "control", 0x8000);
+ }
+
+ device_probe(busdev);
+
+ for (device_find_first_child(busdev, &child);
+ child;
+ device_find_next_child(&child))
+ device_probe(child);
+
+ return 0;
+}
+
+static const struct udevice_id ihs_fpga_ids[] = {
+ { .compatible = "gdsys,iocon_fpga" },
+ { .compatible = "gdsys,iocpu_fpga" },
+ { }
+};
+
+U_BOOT_DRIVER(ihs_fpga_bus) = {
+ .name = "ihs_fpga_bus",
+ .id = UCLASS_IHS_FPGA,
+ .ops = &ihs_fpga_ops,
+ .of_match = ihs_fpga_ids,
+ .probe = ihs_fpga_probe,
+ .priv_auto_alloc_size = sizeof(struct ihs_fpga_priv),
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 2e6498b7dc..56fbedaa9d 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -35,12 +35,14 @@ enum uclass_id {
UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */
UCLASS_DMA, /* Direct Memory Access */
UCLASS_ETH, /* Ethernet device */
+ UCLASS_GDSYS_SOC, /* gdsys soc buses */
UCLASS_GPIO, /* Bank of general-purpose I/O pins */
UCLASS_FIRMWARE, /* Firmware */
UCLASS_I2C, /* I2C bus */
UCLASS_I2C_EEPROM, /* I2C EEPROM device */
UCLASS_I2C_GENERIC, /* Generic I2C device */
UCLASS_I2C_MUX, /* I2C multiplexer */
+ UCLASS_IHS_FPGA, /* gdsys IHS FPGAs */
UCLASS_IRQ, /* Interrupt controller */
UCLASS_KEYBOARD, /* Keyboard input device */
UCLASS_LED, /* Light-emitting diode (LED) */
diff --git a/include/gdsys_soc.h b/include/gdsys_soc.h
new file mode 100644
index 0000000000..2164651f62
--- /dev/null
+++ b/include/gdsys_soc.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2017
+ * Mario Six, Guntermann & Drunck GmbH, mario.six at gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _GDSYS_SOC_H_
+#define _GDSYS_SOC_H_
+
+/**
+ * struct gdsys_soc_child_platdata - platform data for devices on gdsys soc
+ * buses
+ *
+ * To access their register maps, devices on gdsys soc buses usually have
+ * facilitate the accessor function of the IHS FPGA their parent bus is
+ * attached to. To pass the FPGA device down to the bus' children, a pointer to
+ * it is contained in this structure.
+ *
+ * To obtain this structure, use dev_get_parent_platdata(dev) where dev is a
+ * device on the gdsys soc bus.
+ *
+ * @fpga: The IHS FPGA that controls the bus the device is attached to.
+ */
+struct gdsys_soc_child_platdata {
+ struct udevice *fpga;
+};
+
+#endif /* _GDSYS_SOC_H_ */
diff --git a/include/ihs_fpga.h b/include/ihs_fpga.h
new file mode 100644
index 0000000000..552583cbe1
--- /dev/null
+++ b/include/ihs_fpga.h
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2017
+ * Mario Six, Guntermann & Drunck GmbH, mario.six at gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _IHS_FPGA_H_
+#define _IHS_FPGA_H_
+
+/**
+ * struct ihs_fpga_ops - driver operations for IHS FPGA uclass
+ *
+ * Drivers should support these operations unless otherwise noted. These
+ * operations are intended to be used by uclass code, not directly from
+ * other code.
+ */
+struct ihs_fpga_ops {
+ /**
+ * get_reg() - Get value of a named FPGA register
+ *
+ * To accommodate possible future memory layout changes, the registers
+ * of a IHS FPGA are described in the device tree, and each is given a
+ * distinct compatible string to address them with.
+ *
+ * @dev: FPGA device to read from.
+ * @compat: The compatible string of the register to write to.
+ * @value: Pointer to a variable that takes the value read from the
+ * register.
+ * @return 0 if OK, -ENODEV if no named register with the given
+ * compatibility string exists.
+ */
+ int (*get_reg)(struct udevice *dev, const char *compat, uint *value);
+
+ /**
+ * set_reg() - Set value of a named FPGA register
+ *
+ * To accommodate possible future memory layout changes, the registers
+ * of a IHS FPGA are described in the device tree, and each is given a
+ * distinct compatible string to address them with.
+ *
+ * @dev: FPGA device to write to.
+ * @compat: The compatible string of the register to write to.
+ * @value: Value to write to the register.
+ * @return 0 if OK, -ENODEV if no named register with the given
+ * compatibility string exists.
+ */
+ int (*set_reg)(struct udevice *dev, const char *compat, uint value);
+
+ /**
+ * in_le16() - Read 16 bit value from address in FPGA register space
+ *
+ * @dev: FPGA device to read from.
+ * @addr: Address in the FPGA register space to read from.
+ * @return 0 if OK, -ve on error.
+ */
+ u16 (*in_le16)(struct udevice *dev, phys_addr_t addr);
+
+ /**
+ * out_le16() - Write 16 bit value to address in FPGA register space
+ *
+ * @dev: FPGA device to write to.
+ * @addr: Address in the FPGA register space to write to.
+ * @return 0 if OK, -ve on error.
+ */
+ void (*out_le16)(struct udevice *dev, phys_addr_t addr, u16 value);
+};
+
+#define ihs_fpga_get_ops(dev) ((struct ihs_fpga_ops *)(dev)->driver->ops)
+
+/**
+ * fpga_get_reg() - Get value of a named FPGA register
+ *
+ * @dev: FPGA device to read from.
+ * @compat: The compatible string of the register to write to.
+ * @value: Pointer to a variable that takes the value read from the register.
+ * @return 0 if OK, -ENODEV if no named register with the given compatibility
+ * string exists.
+ */
+int fpga_get_reg(struct udevice *dev, const char *compat, uint *value);
+
+/**
+ * fpga_set_reg() - Set value of a named FPGA register
+ *
+ * @dev: FPGA device to write to.
+ * @compat: The compatible string of the register to write to.
+ * @value: Value to write to the register.
+ * @return 0 if OK, -ENODEV if no named register with the given compatibility
+ * string exists.
+ */
+int fpga_set_reg(struct udevice *dev, const char *compat, uint value);
+
+/**
+ * fpga_in_le16() - Read 16 bit value from address in FPGA register space
+ *
+ * @dev: FPGA device to read from.
+ * @addr: Address in the FPGA register space to read from.
+ * @return 0 if OK, -ve on error.
+ */
+u16 fpga_in_le16(struct udevice *dev, phys_addr_t addr);
+
+/**
+ * fpga_out_le16() - Write 16 bit value to address in FPGA register space
+ *
+ * @dev: FPGA device to write to.
+ * @addr: Address in the FPGA register space to write to.
+ * @return 0 if OK, -ve on error.
+ */
+void fpga_out_le16(struct udevice *dev, phys_addr_t addr, u16 value);
+
+#endif /* !_IHS_FPGA_H_ */
--
2.11.0
More information about the U-Boot
mailing list