[U-Boot] [PATCH 49/51] gazerbeam: Import Linux DT
Mario Six
mario.six at gdsys.cc
Fri Jul 14 12:55:35 UTC 2017
Import the Linux device tree for the Gazerbeam board.
Signed-off-by: Mario Six <mario.six at gdsys.cc>
---
arch/powerpc/dts/gazerbeam.dts | 539 +++++++++++++++++++++++++++++
arch/powerpc/dts/gdsys/gazerbeam-base.dtsi | 205 +++++++++++
arch/powerpc/dts/gdsys/mpc8308.dtsi | 243 +++++++++++++
3 files changed, 987 insertions(+)
create mode 100644 arch/powerpc/dts/gazerbeam.dts
create mode 100644 arch/powerpc/dts/gdsys/gazerbeam-base.dtsi
create mode 100644 arch/powerpc/dts/gdsys/mpc8308.dtsi
diff --git a/arch/powerpc/dts/gazerbeam.dts b/arch/powerpc/dts/gazerbeam.dts
new file mode 100644
index 0000000000..35b7af4173
--- /dev/null
+++ b/arch/powerpc/dts/gazerbeam.dts
@@ -0,0 +1,539 @@
+/*
+ * Gazerbeam CON Device Tree Source
+ *
+ * (C) Copyright 2015
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach at gdsys.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/include/ "gdsys/mpc8308.dtsi"
+
+/include/ "gdsys/gazerbeam-base.dtsi"
+
+/ {
+};
+
+&board_lbc {
+ FPGA0:iocon_uart at 1,0 {
+ reg = <0x1 0x0 0x100000>;
+ interrupts = <48 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
+ FPGA1:iocon_uart at 2,0 {
+ reg = <0x2 0x0 0x100000>;
+ interrupts = <17 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+};
+
+&FPGA0 {
+ compatible = "gdsys,iocon_fpga";
+ #gpio-cells = <2>;
+ gpio-controller;
+ bus = <&FPGA0BUS>;
+ unit_id = <0>;
+ fpga-type = <1>;
+ rs232_base = <0x0050>;
+ usb_base = <0x0080>;
+ audio_base = <0x0040>;
+ /*
+ * for every interrupt source there must be a dataset specifying
+ * 1. type (1: standard)
+ * 2. status register offset
+ * 3. mask register offset
+ * 4. default mask
+ */
+ fpga_interrupt_sources =
+ <1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */
+ <1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */
+ /*
+ * for every interrupt there must be a dataset specifying
+ * 1. type (1: status, 2: event)
+ * 2. interrupt source index
+ * 3. interrupt register bit
+ * 4. mask register bit
+ */
+ #fpga_interrupt_map-cells = <4>;
+ fpga_interrupt_map =
+ <1 0 14 14>, /* 0: EXTENDED_INTERRUPT */
+ <1 0 0 0>, /* 1: VIDEO 0 */
+ <1 0 1 1>, /* 2: VIDEO 1 */
+ <1 0 2 2>, /* 3: VIDEO IC 0 */
+ <1 0 3 3>, /* 4: VIDEO IC 1 */
+ <1 0 4 4>, /* 5: IIC MAIN */
+ <1 0 6 6>, /* 6: IIC VIDEO 0 */
+ <1 0 7 7>, /* 7: IIC VIDEO 1 */
+ <1 1 0 0>, /* 8: OSD 0 */
+ <1 1 1 1>, /* 9: OSD 1 */
+ <1 1 2 2>, /* 10: SPDIF 0 */
+ <1 1 3 3>, /* 11: SPDIF 1 */
+ <1 0 12 12>, /* 12: COMM 0 */
+ <1 0 13 13>, /* 13: COMM 1 */
+ <1 0 10 10>, /* 14: COMM 2 */
+ <1 0 11 11>, /* 15: COMM 3 */
+ <2 0 5 5>, /* 16: MDIO */
+ <1 0 8 8>, /* 17: PHY */
+ <1 1 4 4>, /* 18: RS232 */
+ <1 1 5 5>, /* 19: AUDIO */
+ <1 1 8 8>, /* 20: PROC_AUDIO */
+ <1 1 7 7>, /* 21: USB/ETH-UART INT */
+ <2 1 10 10>, /* 22: AXI Bridge 0 */
+ <2 1 11 11>, /* 23: AXI Bridge 1 */
+ <2 1 9 9>, /* 24: USB/ETH-Secondary IIC */
+ <>;
+};
+
+&FPGA1 {
+ compatible = "gdsys,iocon_fpga";
+ #gpio-cells = <2>;
+ gpio-controller;
+ bus = <&FPGA1BUS>;
+ unit_id = <1>;
+ fpga-type = <1>;
+ rs232_base = <0x0050>;
+ usb_base = <0x0070>;
+ audio_base = <0x0040>;
+ /*
+ * for every interrupt source there must be a dataset specifying
+ * 1. type (1: standard)
+ * 2. status register offset
+ * 3. mask register offset
+ * 4. default mask
+ */
+ fpga_interrupt_sources =
+ <1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */
+ <1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */
+ /*
+ * for every interrupt there must be a dataset specifying
+ * 1. type (1: status, 2: event)
+ * 2. interrupt source index
+ * 3. interrupt register bit
+ * 4. mask register bit
+ */
+ #fpga_interrupt_map-cells = <4>;
+ fpga_interrupt_map =
+ <1 0 14 14>, /* 0: EXTENDED_INTERRUPT */
+ <1 0 0 0>, /* 1: VIDEO 0 */
+ <1 0 1 1>, /* 2: VIDEO 1 */
+ <1 0 2 2>, /* 3: VIDEO IC 0 */
+ <1 0 3 3>, /* 4: VIDEO IC 1 */
+ <1 0 4 4>, /* 5: IIC MAIN */
+ <1 0 6 6>, /* 6: IIC VIDEO 0 */
+ <1 0 7 7>, /* 7: IIC VIDEO 1 */
+ <1 1 0 0>, /* 8: OSD 0 */
+ <1 1 1 1>, /* 9: OSD 1 */
+ <1 1 2 2>, /* 10: SPDIF 0 */
+ <1 1 3 3>, /* 11: SPDIF 1 */
+ <1 0 12 12>, /* 12: COMM 0 */
+ <1 0 13 13>, /* 13: COMM 1 */
+ <1 0 10 10>, /* 14: COMM 2 */
+ <1 0 11 11>, /* 15: COMM 3 */
+ <2 0 5 5>, /* 16: MDIO */
+ <1 0 8 8>, /* 17: PHY */
+ <1 1 4 4>, /* 18: RS232 */
+ <1 1 5 5>, /* 19: AUDIO */
+ <1 1 8 8>, /* 20: PROC_AUDIO */
+ <1 1 7 7>, /* 21: USB/ETH-UART INT */
+ <2 1 10 10>, /* 22: AXI Bridge 0 */
+ <2 1 11 11>, /* 23: AXI Bridge 1 */
+ <2 1 9 9>, /* 24: USB/ETH-Secondary IIC */
+ <>;
+};
+
+/ {
+ FPGA0BUS: fpga0bus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x00002000>;
+
+ compatible = "gdsys,soc";
+
+ fpga0_uart_usb {
+ compatible = "gdsys,ihs_simple_uart";
+ reg = <0xa0 0x08>;
+ fpga_interrupts = <21>;
+ line = <0>;
+ };
+
+ fpga0_iic_main {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0x60 0x10>;
+ fpga_interrupts = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga0_dp_video0_redriver: fpga0_dp_video0_redriver {
+ compatible = "ti,sn75dp130";
+ reg = <0x2c>;
+ eq-i2c-enable = <3 2 1 0
+ 3 2 1 0
+ 3 2 1 0
+ 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
+ };
+ fpga0_dp_video1_redriver: fpga0_dp_video1_redriver {
+ compatible = "ti,sn75dp130";
+ reg = <0x2e>;
+ eq-i2c-enable = <3 2 1 0
+ 3 2 1 0
+ 3 2 1 0
+ 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
+ };
+ lm77 at 48 {
+ compatible = "national,lm77";
+ reg = <0x48>;
+ };
+ ads1015 at 49 {
+ compatible = "ti,ads1015";
+ reg = <0x49>;
+ };
+ ads1015 at 4b {
+ compatible = "ti,ads1015";
+ reg = <0x4b>;
+ };
+ };
+
+ fpga0_video0 {
+ compatible = "gdsys,ihs_video_out";
+ reg = <0x100 0x40>;
+ fpga_interrupts = <1 8>; /* VIDEO OSD */
+ osd_base = <0x180>;
+ osd_buffer_base = <0x1000>;
+ video_id = <0>;
+ fpga-force-pos-pol;
+ sync-source;
+ dp_tx = <&fpga0_dp_video0>;
+ clk_gen = <&fpga0_video0_clkgen>;
+ };
+
+ fpga0_iic_video0 {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0x1c0 0x10>;
+ fpga_interrupts = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga0_video0_clkgen: fpga0_video0_clkgen {
+ compatible = "idt,ics8n3qv01";
+ reg = <0x6e>;
+ channel = <0>;
+ };
+ };
+
+ fpga0_axi_video0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "gdsys,ihs_axi";
+ reg = <0x170 0x10>;
+ fpga_interrupts = <22>;
+
+ fpga0_dp_video0: fpga0_dp_video0 {
+ compatible = "gdsys,logicore_dp_tx";
+ reg = <0x44a10000 0x1000>;
+ redriver = <&fpga0_dp_video0_redriver>;
+ video_id = <0>;
+ };
+ };
+
+ fpga0_video1 {
+ compatible = "gdsys,ihs_video_out";
+ reg = <0x200 0x40>;
+ fpga_interrupts = <2 9>; /* VIDEO OSD */
+ osd_base = <0x280>;
+ osd_buffer_base = <0x2000>;
+ video_id = <1>;
+ fpga-force-pos-pol;
+ sync-source;
+ dp_tx = <&fpga0_dp_video1>;
+ clk_gen = <&fpga0_video1_clkgen>;
+ };
+
+ fpga0_iic_video1 {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0x2c0 0x10>;
+ fpga_interrupts = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga0_video1_clkgen: fpga0_video1_clkgen {
+ compatible = "idt,ics8n3qv01";
+ reg = <0x6e>;
+ channel = <1>;
+ };
+ };
+
+ fpga0_axi_video1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "gdsys,ihs_axi";
+ reg = <0x270 0x10>;
+ fpga_interrupts = <23>;
+
+ fpga0_dp_video1: fpga0_dp_video1 {
+ compatible = "gdsys,logicore_dp_tx";
+ reg = <0x44a10000 0x1000>;
+ redriver = <&fpga0_dp_video1_redriver>;
+ video_id = <1>;
+ };
+ };
+
+ fpga0_iic_usb {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0xb0 0x10>;
+ fpga_interrupts = <24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9555 at 20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+ };
+
+ fpga0_ep0 {
+ compatible = "gdsys,io-endpoint";
+ reg = < 0x020 0x10
+ 0x320 0x10
+ 0x340 0x10
+ 0x360 0x10>;
+ irq-model-local;
+ fpga_interrupts = <12 13 14 15>;
+ pollcycle = <200>;
+ nprot_channel = <16>;
+ uart_line = <0>;
+ ep_index = <0>;
+ line_protocol = <1>;
+ };
+
+ fpga0_mdio {
+ compatible = "gdsys,ihs_mdiomaster";
+ reg = <0x0058 0x10>;
+ fpga_interrupts = <16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga0_phy0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <0>;
+ };
+ fpga0_phy1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <1>;
+ };
+ fpga0_phy2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <2>;
+ };
+ fpga0_phy3 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <3>;
+ };
+ };
+
+ };
+
+
+ FPGA1BUS: fpga1bus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x00002000>;
+
+ compatible = "gdsys,soc";
+
+ fpga1_uart_usb {
+ compatible = "gdsys,ihs_simple_uart";
+ reg = <0xa0 0x08>;
+ fpga_interrupts = <21>;
+ line = <4>; /* TODO check and FIX */
+ };
+
+ fpga1_iic_main {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0x60 0x10>;
+ fpga_interrupts = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga1_dp_video0_redriver: fpga1_dp_video0_redriver {
+ compatible = "ti,sn75dp130";
+ reg = <0x2c>;
+ eq-i2c-enable = <3 2 1 0
+ 3 2 1 0
+ 3 2 1 0
+ 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
+ };
+ fpga1_dp_video1_redriver: fpga1_dp_video1_redriver {
+ compatible = "ti,sn75dp130";
+ reg = <0x2e>;
+ eq-i2c-enable = <3 2 1 0
+ 3 2 1 0
+ 3 2 1 0
+ 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
+ };
+ lm77 at 48 {
+ compatible = "national,lm77";
+ reg = <0x48>;
+ };
+ ads1015 at 49 {
+ compatible = "ti,ads1015";
+ reg = <0x49>;
+ };
+ ads1015 at 4b {
+ compatible = "ti,ads1015";
+ reg = <0x4b>;
+ };
+ };
+
+ fpga1_video0 {
+ compatible = "gdsys,ihs_video_out";
+ reg = <0x100 0x40>;
+ fpga_interrupts = <1 8>; /* VIDEO OSD */
+ osd_base = <0x180>;
+ osd_buffer_base = <0x1000>;
+ video_id = <4>;
+ fpga-force-pos-pol;
+ dp_tx = <&fpga1_dp_video0>;
+ clk_gen = <&fpga1_video0_clkgen>;
+ };
+
+ fpga1_iic_video0 {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0x1c0 0x10>;
+ fpga_interrupts = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga1_video0_clkgen: fpga1_video0_clkgen {
+ compatible = "idt,ics8n3qv01";
+ reg = <0x6e>;
+ channel = <4>;
+ };
+ };
+
+ fpga1_axi_video0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "gdsys,ihs_axi";
+ reg = <0x170 0x10>;
+ fpga_interrupts = <22>;
+
+ fpga1_dp_video0: fpga1_dp_video0 {
+ compatible = "gdsys,logicore_dp_tx";
+ reg = <0x44a10000 0x1000>;
+ redriver = <&fpga1_dp_video0_redriver>;
+ video_id = <4>;
+ };
+ };
+
+ fpga1_video1 {
+ compatible = "gdsys,ihs_video_out";
+ reg = <0x200 0x40>;
+ fpga_interrupts = <2 9>; /* VIDEO OSD */
+ osd_base = <0x280>;
+ osd_buffer_base = <0x2000>;
+ video_id = <5>;
+ dp_tx = <&fpga1_dp_video1>;
+ clk_gen = <&fpga1_video1_clkgen>;
+ };
+
+ fpga1_iic_video1 {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0x2c0 0x10>;
+ fpga_interrupts = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga1_video1_clkgen: fpga1_video1_clkgen {
+ compatible = "idt,ics8n3qv01";
+ reg = <0x6e>;
+ channel = <5>;
+ };
+ };
+
+ fpga1_axi_video1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "gdsys,ihs_axi";
+ reg = <0x270 0x10>;
+ fpga_interrupts = <23>;
+
+ fpga1_dp_video1: fpga1_dp_video1 {
+ compatible = "gdsys,logicore_dp_tx";
+ reg = <0x44a10000 0x1000>;
+ redriver = <&fpga1_dp_video1_redriver>;
+ video_id = <5>;
+ };
+ };
+
+ fpga1_iic_usb {
+ compatible = "gdsys,ihs_i2cmaster";
+ reg = <0xb0 0x10>;
+ fpga_interrupts = <24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9555 at 20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+ };
+
+ fpga1_ep0 {
+ compatible = "gdsys,io-endpoint";
+ reg = < 0x020 0x10
+ 0x320 0x10
+ 0x340 0x10
+ 0x360 0x10>;
+ irq-model-local;
+ fpga_interrupts = <12 13 14 15>;
+ pollcycle = <200>;
+ nprot_channel = <17>;
+ uart_line = <1>;
+ ep_index = <0>;
+ line_protocol = <1>;
+ };
+
+ fpga1_mdio {
+ compatible = "gdsys,ihs_mdiomaster";
+ reg = <0x0058 0x10>;
+ fpga_interrupts = <16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga1_phy0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <0>;
+ };
+ fpga1_phy1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <1>;
+ };
+ fpga1_phy2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <2>;
+ };
+ fpga1_phy3 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type ="ethernet-phy";
+ reg = <3>;
+ };
+ };
+
+ };
+
+};
diff --git a/arch/powerpc/dts/gdsys/gazerbeam-base.dtsi b/arch/powerpc/dts/gdsys/gazerbeam-base.dtsi
new file mode 100644
index 0000000000..9382107186
--- /dev/null
+++ b/arch/powerpc/dts/gdsys/gazerbeam-base.dtsi
@@ -0,0 +1,205 @@
+/*
+ * Gazerbeam Device Tree Source
+ *
+ * (C) Copyright 2015
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach at gdsys.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/ {
+ model = "gdsys,gazerbeam";
+ compatible = "fsl,mpc8308rdb";
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ chosen {
+ stdout-path = "/immr at e0000000/serial at 4600";
+ };
+};
+
+&board_lbc {
+ ranges = <0x0 0x0 0xfe000000 0x00800000
+ 0x1 0x0 0xe0600000 0x00003000
+ 0x2 0x0 0xe0700000 0x00003000>;
+
+ flash at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x100000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ u-boot at 0 {
+ reg = <0x0 0x60000>;
+ };
+ env at 60000 {
+ reg = <0x60000 0x10000>;
+ };
+ env1 at 70000 {
+ reg = <0x70000 0x10000>;
+ };
+ spare at 80000 {
+ reg = <0x80000 0x80000>;
+ };
+ };
+};
+
+&enet1 {
+ status = "okay";
+};
+
+&IIC {
+ fsl,preserve-clocking;
+
+ at97sc3205t at 29 {
+ compatible = "atmel,at97sc3204t";
+ reg = <0x29>;
+ };
+
+ lm77 at 48 {
+ compatible = "national,lm77";
+ reg = <0x48>;
+ };
+
+ ads1015 at 49 {
+ compatible = "ti,ads1015";
+ reg = <0x49>;
+ };
+
+ lm77 at 4a {
+ compatible = "national,lm77";
+ reg = <0x4a>;
+ };
+
+ emc2305 at 4c {
+ compatible = "smsc,emc2305";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4c>;
+ fan at 0 {
+ reg = <0>;
+ };
+ fan at 1 {
+ reg = <1>;
+ };
+ fan at 2 {
+ reg = <2>;
+ };
+ fan at 3 {
+ reg = <3>;
+ };
+ fan at 4 {
+ reg = <4>;
+ };
+ };
+
+ cs4265 at 4f {
+ compatible = "cirrus,cs4265";
+ reg = <0x0000004f>;
+ };
+
+ at24c512 at 54 {
+ compatible = "atmel,24c512";
+ reg = <0x54>;
+ };
+
+ ds1339 at 68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+
+ /* PPC-Board */
+ pca9698 at 22 {
+ compatible = "nxp,pca9698";
+ reg = <0x22>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ /* IO-Board */
+ pca9698 at 20 {
+ compatible = "nxp,pca9698";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+};
+
+&IIC2 {
+ fsl,preserve-clocking;
+
+ status = "okay";
+
+ /* MC2/SC-Board */
+ GPIO_VB0: pca9698 at 20 {
+ compatible = "nxp,pca9698";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ /* MC4-Board */
+ GPIO_VB1: pca9698 at 22 {
+ compatible = "nxp,pca9698";
+ reg = <0x22>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+};
+
+&SPI {
+ gpios = < /*SPI-CSS-FPGA-U-FLASH#*/ &gpio0 8 0
+ /*SPI-CSS-FPGA-O-FLASH#*/ &gpio0 6 0
+ /*SPI-CSS-STDP1_U-FLASH#*/ &gpio0 12 0
+ /*SPI-CSS-STDP2_U-FLASH#*/ &gpio0 11 0
+ /*SPI-CSS-STDP1_O-FLASH#*/ &gpio0 15 0
+ /*SPI-CSS-STDP2_O-FLASH#*/ &gpio0 3 0>;
+
+ m25p16 at 0 {
+ compatible = "st,n25q128a11";
+ reg = <0x0>;
+ spi-max-frequency = <20000000>;
+ };
+
+ m25p16 at 1 {
+ compatible = "st,n25q128a11";
+ reg = <0x1>;
+ spi-max-frequency = <20000000>;
+ };
+
+ m25p16 at 2 {
+ compatible = "st,m25p40";
+ reg = <0x2>;
+ spi-max-frequency = <20000000>;
+ };
+
+ m25p16 at 3 {
+ compatible = "st,m25p40";
+ reg = <0x3>;
+ spi-max-frequency = <20000000>;
+ };
+
+ m25p16 at 4 {
+ compatible = "st,m25p40";
+ reg = <0x4>;
+ spi-max-frequency = <20000000>;
+ };
+
+ m25p16 at 5 {
+ compatible = "st,m25p40";
+ reg = <0x5>;
+ spi-max-frequency = <20000000>;
+ };
+};
diff --git a/arch/powerpc/dts/gdsys/mpc8308.dtsi b/arch/powerpc/dts/gdsys/mpc8308.dtsi
new file mode 100644
index 0000000000..61017fdb02
--- /dev/null
+++ b/arch/powerpc/dts/gdsys/mpc8308.dtsi
@@ -0,0 +1,243 @@
+/*
+ * Basic platform for gdsys mpc8308 based devices
+ *
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach at gdsys.de
+ *
+ * based on mpc8308rdb
+ * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8308 at 0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <16384>;
+ i-cache-size = <16384>;
+ timebase-frequency = <0>; // from bootloader
+ bus-frequency = <0>; // from bootloader
+ clock-frequency = <0>; // from bootloader
+ };
+ };
+
+ board_lbc: localbus at e0005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
+ reg = <0xe0005000 0x1000>;
+ interrupts = <77 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
+ board_soc: immr at e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,mpc8308-immr", "simple-bus";
+ ranges = <0 0xe0000000 0x00100000>;
+ reg = <0xe0000000 0x00000200>;
+ bus-frequency = <0>;
+
+ wdt at 200 {
+ device_type = "watchdog";
+ compatible = "mpc83xx_wdt";
+ reg = <0x200 0x100>;
+ };
+
+ IIC:i2c at 3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <14 0x8>;
+ interrupt-parent = <&ipic>;
+ dfsrr;
+ };
+
+ IIC2: i2c at 3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <15 0x8>;
+ interrupt-parent = <&ipic>;
+ dfsrr;
+ status = "disabled";
+ };
+
+ SPI:spi at 7000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl,spi";
+ reg = <0x7000 0x1000>;
+ interrupts = <16 0x8>;
+ interrupt-parent = <&ipic>;
+ mode = "cpu";
+ };
+
+ sdhc at 2e000 {
+ compatible = "fsl,esdhc", "fsl,mpc8308-esdhc";
+ reg = <0x2e000 0x1000>;
+ interrupts = <42 0x2>;
+ interrupt-parent = <&ipic>;
+ sdhci,auto-cmd12;
+ /* Filled in by U-Boot */
+ clock-frequency = <0>;
+ };
+
+ serial0: serial at 4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <133333333>;
+ interrupts = <9 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
+ serial1: serial at 4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <133333333>;
+ interrupts = <10 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
+ gpio0: gpio at c00 {
+ #gpio-cells = <2>;
+ device_type = "gpio";
+ compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
+ reg = <0xc00 0x18>;
+ interrupts = <74 0x8>;
+ interrupt-parent = <&ipic>;
+ gpio-controller;
+ };
+
+ /* IPIC
+ * interrupts cell = <intr #, sense>
+ * sense values match linux IORESOURCE_IRQ_* defines:
+ * sense == 8: Level, low assertion
+ * sense == 2: Edge, high-to-low change
+ */
+ ipic: interrupt-controller at 700 {
+ compatible = "fsl,ipic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x700 0x100>;
+ device_type = "ipic";
+ };
+
+ ipic-msi at 7c0 {
+ compatible = "fsl,ipic-msi";
+ reg = <0x7c0 0x40>;
+ msi-available-ranges = <0x0 0x100>;
+ interrupts = < 0x43 0x8
+ 0x4 0x8
+ 0x51 0x8
+ 0x52 0x8
+ 0x56 0x8
+ 0x57 0x8
+ 0x58 0x8
+ 0x59 0x8 >;
+ interrupt-parent = < &ipic >;
+ };
+
+ dma at 2c000 {
+ compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";
+ reg = <0x2c000 0x1800>;
+ interrupts = <3 0x8
+ 94 0x8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ enet0: ethernet at 24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x24000 0x1000>;
+
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <32 0x8 33 0x8 34 0x8>;
+ interrupt-parent = <&ipic>;
+ tbi-handle = < &tbi0 >;
+ phy-handle = < &phy1 >;
+ fsl,magic-packet;
+
+ mdio at 520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x520 0x20>;
+ phy1: ethernet-phy at 1 {
+ reg = <0x1>;
+ };
+ phy2: ethernet-phy at 0 {
+ reg = <0x0>;
+ device_type = "ethernet-phy";
+ };
+ tbi0: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ enet1: ethernet at 25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 0x8 36 0x8 37 0x8>;
+ interrupt-parent = <&ipic>;
+ phy-handle = < &phy2 >;
+ status = "disabled";
+
+ mdio at 520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+ tbi1: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+ };
+};
--
2.11.0
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