[U-Boot] [PATCH] PCI: layerscape: Fix the bug assigning wrong address to LS2088A pcie cfg1 space

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>

This bug is brought by the commit 3d8553f0a3 (pci: layerscape: add
LS2088A series SoC pcie support), which only updated cfg_res.start
and did not update the .end field, this will make fdt_resource_size()
getting wrong value when calculate the cfg1 space address. This
patch is to fix the bug.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
---
 drivers/pci/pcie_layerscape.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 7565e2f..007b84c 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -474,6 +474,7 @@ static int ls_pcie_probe(struct udevice *dev)
 	bool ep_mode;
 	uint svr;
 	int ret;
+	fdt_size_t cfg_size;
 
 	pcie->bus = dev;
 
@@ -535,8 +536,10 @@ static int ls_pcie_probe(struct udevice *dev)
 	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
 	    svr == SVR_LS2048A || svr == SVR_LS2044A ||
 	    svr == SVR_LS2081A || svr == SVR_LS2041A) {
+		cfg_size = fdt_resource_size(&pcie->cfg_res);
 		pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
 					LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+		pcie->cfg_res.end = pcie->cfg_res.start + cfg_size;
 		pcie->ctrl = pcie->lut + 0x40000;
 	}
 
-- 
2.1.0.27.g96db324